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-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simout10
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt32
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt32
6 files changed, 68 insertions, 20 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 917f45398..451406111 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index d54aada3a..843c8c748 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:37:09
-M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 18:44:04
+M5 executing on aus-bc3-b4
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 8b5b713cb..d9333fa95 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2664701 # Simulator instruction rate (inst/s)
-host_mem_usage 209976 # Number of bytes of host memory used
-host_seconds 37.09 # Real time elapsed on the host
-host_tick_rate 1429827283 # Simulator tick rate (ticks/s)
+host_inst_rate 2790357 # Simulator instruction rate (inst/s)
+host_mem_usage 261760 # Number of bytes of host memory used
+host_seconds 35.42 # Real time elapsed on the host
+host_tick_rate 1497251955 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 98838077 # Number of instructions simulated
sim_seconds 0.053035 # Number of seconds simulated
sim_ticks 53034982000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 631dd37fd..1d235cb1e 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 935e56759..8e789b6bf 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 20 2010 15:04:50
-M5 revision 0c4a7d867247 7686 default qtip print-identical tip
-M5 started Sep 20 2010 15:04:54
-M5 executing on phenom
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 18:37:39
+M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index eb164565e..595ab3b43 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1323688 # Simulator instruction rate (inst/s)
-host_mem_usage 204612 # Number of bytes of host memory used
-host_seconds 74.03 # Real time elapsed on the host
-host_tick_rate 1797531911 # Simulator tick rate (ticks/s)
+host_inst_rate 607999 # Simulator instruction rate (inst/s)
+host_mem_usage 269484 # Number of bytes of host memory used
+host_seconds 161.18 # Real time elapsed on the host
+host_tick_rate 825650483 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
sim_seconds 0.133079 # Number of seconds simulated
@@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 46870204 # To
system.cpu.dcache.warmup_cycle 1079223000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 122819 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses