diff options
Diffstat (limited to 'tests/long/50.vortex/ref/arm/linux')
10 files changed, 126 insertions, 38 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index d32286142..2381c9471 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 4650e6a0c..93fbb5edc 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 18 2011 03:54:36 -M5 revision 218f733923f8 7861 default qtip int/arm_gdb.patch tip -M5 started Jan 18 2011 04:19:02 -M5 executing on aus-bc2-b9 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index c8769189d..ca56969f4 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 156565 # Simulator instruction rate (inst/s) -host_mem_usage 260328 # Number of bytes of host memory used -host_seconds 631.29 # Real time elapsed on the host -host_tick_rate 93871242 # Simulator tick rate (ticks/s) +host_inst_rate 60156 # Simulator instruction rate (inst/s) +host_mem_usage 246816 # Number of bytes of host memory used +host_seconds 1643.03 # Real time elapsed on the host +host_tick_rate 36067570 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 98838077 # Number of instructions simulated sim_seconds 0.059260 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 114018884 # Number of insts commited each cycle system.cpu.commit.COM:count 98838077 # Number of instructions committed +system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 89710266 # Number of committed integer instructions. system.cpu.commit.COM:loads 27315295 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 47871033 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 117533456 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 40 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 12122688 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 12759.423411 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 9476.994450 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 2833293 # system.cpu.iew.memOrderViolationEvents 39532 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1768227 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 860228 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 255816186 # number of integer regfile reads +system.cpu.int_regfile_writes 78479487 # number of integer regfile writes system.cpu.ipc 0.833936 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.833936 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 117533456 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.920997 # Inst issue rate +system.cpu.iq.fp_alu_accesses 187 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 568 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 110479458 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 337237563 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 104978377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 134232957 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 116084938 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 109156507 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1016199 # Number of non-speculative instructions added to the IQ @@ -473,7 +488,11 @@ system.cpu.memDep0.conflictingLoads 7990320 # Nu system.cpu.memDep0.conflictingStores 10924699 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 32508348 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 23389031 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 153116651 # number of misc regfile reads +system.cpu.misc_regfile_writes 1948149 # number of misc regfile writes system.cpu.numCycles 118519960 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1866194 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 74745628 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1883 # Number of times rename has blocked due to IQ full @@ -487,10 +506,14 @@ system.cpu.rename.RENAME:RunCycles 68672790 # Nu system.cpu.rename.RENAME:SquashCycles 3514572 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1591233 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 18613027 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 83717 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 333328918 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 11499162 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 818368 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 3724500 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 819368 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 229794357 # The number of ROB reads +system.cpu.rob.rob_writes 237655572 # The number of ROB writes system.cpu.timesIdled 60726 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini index 451406111..d284ed163 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout index 843c8c748..4cf2e23b7 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:44:04 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt index d9333fa95..a170aadf3 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2790357 # Simulator instruction rate (inst/s) -host_mem_usage 261760 # Number of bytes of host memory used -host_seconds 35.42 # Real time elapsed on the host -host_tick_rate 1497251955 # Simulator tick rate (ticks/s) +host_inst_rate 986864 # Simulator instruction rate (inst/s) +host_mem_usage 237100 # Number of bytes of host memory used +host_seconds 100.15 # Real time elapsed on the host +host_tick_rate 529534290 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 98838077 # Number of instructions simulated sim_seconds 0.053035 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 106069965 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 106069965 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 98838077 # Number of instructions executed -system.cpu.num_refs 47871034 # Number of memory references +system.cpu.num_int_alu_accesses 89710267 # Number of integer alu accesses +system.cpu.num_int_insts 89710267 # number of integer instructions +system.cpu.num_int_register_reads 258410605 # number of times the integer registers were read +system.cpu.num_int_register_writes 73280343 # number of times the integer registers were written +system.cpu.num_load_insts 27315295 # Number of load instructions +system.cpu.num_mem_refs 47871034 # number of memory refs +system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini index 1d235cb1e..0e5c2c18c 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr index eabe42249..e391217dd 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout index 8e789b6bf..54e01817e 100755 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt index 595ab3b43..b20318b2f 100644 --- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 607999 # Simulator instruction rate (inst/s) -host_mem_usage 269484 # Number of bytes of host memory used -host_seconds 161.18 # Real time elapsed on the host -host_tick_rate 825650483 # Simulator tick rate (ticks/s) +host_inst_rate 430473 # Simulator instruction rate (inst/s) +host_mem_usage 244816 # Number of bytes of host memory used +host_seconds 227.65 # Real time elapsed on the host +host_tick_rate 584574230 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 97997303 # Number of instructions simulated sim_seconds 0.133079 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 88450 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 266157390 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 266157390 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses +system.cpu.num_fp_insts 56 # number of float instructions +system.cpu.num_fp_register_reads 36 # number of times the floating registers were read +system.cpu.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 97997303 # Number of instructions executed -system.cpu.num_refs 47871034 # Number of memory references +system.cpu.num_int_alu_accesses 89710267 # Number of integer alu accesses +system.cpu.num_int_insts 89710267 # number of integer instructions +system.cpu.num_int_register_reads 285424208 # number of times the integer registers were read +system.cpu.num_int_register_writes 73333595 # number of times the integer registers were written +system.cpu.num_load_insts 27315295 # Number of load instructions +system.cpu.num_mem_refs 47871034 # number of memory refs +system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- |