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-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt18
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simout6
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt12
4 files changed, 22 insertions, 22 deletions
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 2dc10edc6..d54aada3a 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 25 2010 20:52:35
-M5 revision ffac9df60637 7512 default tip
-M5 started Jul 26 2010 23:53:12
+M5 compiled Aug 24 2010 15:34:40
+M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
+M5 started Aug 24 2010 15:37:09
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 52792656500 because target called exit()
+Exiting @ tick 53034982000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 54b57c099..8b5b713cb 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4246205 # Simulator instruction rate (inst/s)
-host_mem_usage 204740 # Number of bytes of host memory used
-host_seconds 23.16 # Real time elapsed on the host
-host_tick_rate 2279192640 # Simulator tick rate (ticks/s)
+host_inst_rate 2664701 # Simulator instruction rate (inst/s)
+host_mem_usage 209976 # Number of bytes of host memory used
+host_seconds 37.09 # Real time elapsed on the host
+host_tick_rate 1429827283 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 98353426 # Number of instructions simulated
-sim_seconds 0.052793 # Number of seconds simulated
-sim_ticks 52792656500 # Number of ticks simulated
+sim_insts 98838077 # Number of instructions simulated
+sim_seconds 0.053035 # Number of seconds simulated
+sim_ticks 53034982000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 105585314 # number of cpu cycles simulated
-system.cpu.num_insts 98353426 # Number of instructions executed
+system.cpu.numCycles 106069965 # number of cpu cycles simulated
+system.cpu.num_insts 98838077 # Number of instructions executed
system.cpu.num_refs 47871034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 0a6111213..7aba6f5e0 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 25 2010 20:52:35
-M5 revision ffac9df60637 7512 default tip
-M5 started Jul 26 2010 23:59:20
+M5 compiled Aug 24 2010 15:34:40
+M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
+M5 started Aug 24 2010 15:39:36
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 7ded93bcd..b085aeacb 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1206944 # Simulator instruction rate (inst/s)
-host_mem_usage 212432 # Number of bytes of host memory used
-host_seconds 80.79 # Real time elapsed on the host
-host_tick_rate 1653060218 # Simulator tick rate (ticks/s)
+host_inst_rate 1745846 # Simulator instruction rate (inst/s)
+host_mem_usage 217668 # Number of bytes of host memory used
+host_seconds 56.13 # Real time elapsed on the host
+host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 97512652 # Number of instructions simulated
+sim_insts 97997303 # Number of instructions simulated
sim_seconds 0.133556 # Number of seconds simulated
sim_ticks 133556162000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
@@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 88579 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 267112324 # number of cpu cycles simulated
-system.cpu.num_insts 97512652 # Number of instructions executed
+system.cpu.num_insts 97997303 # Number of instructions executed
system.cpu.num_refs 47871034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls