diff options
Diffstat (limited to 'tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt | 227 |
1 files changed, 122 insertions, 105 deletions
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index bf74220de..e924e185b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480067 # Simulator instruction rate (inst/s) -host_mem_usage 157016 # Number of bytes of host memory used -host_seconds 283.81 # Real time elapsed on the host -host_tick_rate 698858124 # Simulator tick rate (ticks/s) +host_inst_rate 1128502 # Simulator instruction rate (inst/s) +host_mem_usage 210664 # Number of bytes of host memory used +host_seconds 120.73 # Real time elapsed on the host +host_tick_rate 1658768570 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.198342 # Number of seconds simulated -sim_ticks 198341876000 # Number of ticks simulated +sim_seconds 0.200268 # Number of seconds simulated +sim_ticks 200267857000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 964329000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 873351000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20754892 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2735300000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 109412 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2516476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 109412 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. @@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency -system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 23883.829026 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency +system.cpu.dcache.demand_hits 57940704 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3699629000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses +system.cpu.dcache.demand_misses 154901 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 3389827000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 154901 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23883.829026 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_misses 150663 # number of overall misses +system.cpu.dcache.overall_hits 57940704 # number of overall hits +system.cpu.dcache.overall_miss_latency 3699629000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses +system.cpu.dcache.overall_misses 154901 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 3389827000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 154901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.106244 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 584597000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2006.859894 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 142624255000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2314158000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 105189 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1157079000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 105189 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 232513 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 191480 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 902726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.176476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 41033 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 451363000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 41033 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 4263 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.875205 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 93632000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 4263 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46893000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 4263 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 107279 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 107279 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.315911 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 191480 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3216884000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.432991 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 146222 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1608442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.432991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 146222 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 135187 # number of overall misses +system.cpu.l2cache.overall_hits 191480 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3216884000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.432991 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 146222 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1608442000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.432991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 146222 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 101911 # number of replacements -system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 22010 # number of replacements +system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use -system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 82918 # number of writebacks +system.cpu.l2cache.tagsinuse 6146.860431 # Cycle average of tags in use +system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 198341876000 # number of cpu cycles simulated +system.cpu.numCycles 200267857000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls |