diff options
Diffstat (limited to 'tests/long/50.vortex/ref/sparc/linux')
6 files changed, 74 insertions, 24 deletions
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 51965dbb5..0962890e6 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index 27a5cc38b..7f5789393 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:33:19 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:11 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index b6b56aac5..d6bfda298 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1397341 # Simulator instruction rate (inst/s) -host_mem_usage 194632 # Number of bytes of host memory used -host_seconds 97.43 # Real time elapsed on the host -host_tick_rate 699480350 # Simulator tick rate (ticks/s) +host_inst_rate 1204089 # Simulator instruction rate (inst/s) +host_mem_usage 228576 # Number of bytes of host memory used +host_seconds 113.06 # Real time elapsed on the host +host_tick_rate 602742669 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 68148678500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 136297358 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 136297358 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references +system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read +system.cpu.num_int_register_writes 113225733 # number of times the integer registers were written +system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160249 # number of memory refs +system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 08b8aa7ee..8ec9f75ef 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex +executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index e214aaa33..b27952d03 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:35:02 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:39 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index d33aa6f85..eb6eca0bd 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1222037 # Simulator instruction rate (inst/s) -host_mem_usage 206136 # Number of bytes of host memory used -host_seconds 111.40 # Real time elapsed on the host -host_tick_rate 1821674437 # Simulator tick rate (ticks/s) +host_inst_rate 463084 # Simulator instruction rate (inst/s) +host_mem_usage 236284 # Number of bytes of host memory used +host_seconds 293.98 # Real time elapsed on the host +host_tick_rate 690315679 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.202942 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 87265 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 405883984 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 405883984 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.num_fp_insts 2326977 # number of float instructions +system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 136139203 # Number of instructions executed -system.cpu.num_refs 58160249 # Number of memory references +system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses +system.cpu.num_int_insts 115187758 # number of integer instructions +system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read +system.cpu.num_int_register_writes 113225732 # number of times the integer registers were written +system.cpu.num_load_insts 37275868 # Number of load instructions +system.cpu.num_mem_refs 58160249 # number of memory refs +system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls ---------- End Simulation Statistics ---------- |