diff options
Diffstat (limited to 'tests/long/50.vortex/ref/sparc/linux')
4 files changed, 62 insertions, 60 deletions
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index a0a6eb4e4..01fab79ce 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -152,6 +152,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -181,6 +182,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 667657de7..89c35043c 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 595046 # Simulator instruction rate (inst/s) -host_mem_usage 168184 # Number of bytes of host memory used -host_seconds 228.79 # Real time elapsed on the host -host_tick_rate 875480121 # Simulator tick rate (ticks/s) +host_inst_rate 809753 # Simulator instruction rate (inst/s) +host_mem_usage 216324 # Number of bytes of host memory used +host_seconds 168.12 # Real time elapsed on the host +host_tick_rate 1194295397 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.200299 # Number of seconds simulated -sim_ticks 200299240000 # Number of ticks simulated +sim_seconds 0.200790 # Number of seconds simulated +sim_ticks 200790381000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20034.528231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18034.528231 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 911551000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 820553000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2735125000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2516315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23541.522491 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3646676000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3336868000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23541.522491 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 3646676000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3336868000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.107061 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 584692000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13838.865600 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11838.865600 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2588200000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2214152000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13838.865600 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2588200000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2214152000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13838.865600 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 2588200000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2214152000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.879224 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 142655430000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2313938000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 874412000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21907.172996 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 93456000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles @@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3188350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 192777 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3188350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses system.cpu.l2cache.overall_misses 144925 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19343.330573 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 400598480 # number of cpu cycles simulated +system.cpu.numCycles 401580762 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index 059f14554..b5ea49da4 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index c5f2dbeb0..5b4fb94a9 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -1,13 +1,13 @@ M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 13 2008 00:33:29 -M5 started Wed Feb 13 18:35:08 2008 -M5 executing on zizzer +M5 compiled Feb 24 2008 13:27:50 +M5 started Mon Feb 25 16:16:46 2008 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200299240000 because target called exit() +Exiting @ tick 200790381000 because target called exit() |