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-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt40
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt40
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt40
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-atomic/simout10
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt8
15 files changed, 125 insertions, 77 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 2927f396f..bf2f959df 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 3c4f7e5f4..dc258abe3 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:23:18
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:36:30
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index c3cb349a5..9dcaad468 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 261905 # Simulator instruction rate (inst/s)
-host_mem_usage 216920 # Number of bytes of host memory used
-host_seconds 303.90 # Real time elapsed on the host
-host_tick_rate 89289765 # Simulator tick rate (ticks/s)
+host_inst_rate 259851 # Simulator instruction rate (inst/s)
+host_mem_usage 216888 # Number of bytes of host memory used
+host_seconds 306.30 # Real time elapsed on the host
+host_tick_rate 88589448 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 19520694 # Nu
system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 36599689 # DTB accesses
-system.cpu.dtb.acv 39 # DTB access violations
-system.cpu.dtb.hits 36425481 # DTB hits
-system.cpu.dtb.misses 174208 # DTB misses
+system.cpu.dtb.data_accesses 36599689 # DTB accesses
+system.cpu.dtb.data_acv 39 # DTB access violations
+system.cpu.dtb.data_hits 36425481 # DTB hits
+system.cpu.dtb.data_misses 174208 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 21541288 # DTB read accesses
system.cpu.dtb.read_acv 37 # DTB read access violations
system.cpu.dtb.read_hits 21383020 # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 9777311 # Nu
system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 13412237 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 13386072 # ITB hits
-system.cpu.itb.misses 26165 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 13412237 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 13386072 # ITB hits
+system.cpu.itb.fetch_misses 26165 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 5a410e8c9..31e1868d0 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 7f58d408c..cac080f34 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:31:50
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:43:53
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 3b23e3386..25afd1229 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5386925 # Simulator instruction rate (inst/s)
-host_mem_usage 205832 # Number of bytes of host memory used
-host_seconds 16.40 # Real time elapsed on the host
-host_tick_rate 2696520513 # Simulator tick rate (ticks/s)
+host_inst_rate 5274353 # Simulator instruction rate (inst/s)
+host_mem_usage 207596 # Number of bytes of host memory used
+host_seconds 16.75 # Real time elapsed on the host
+host_tick_rate 2640164541 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
-system.cpu.dtb.accesses 34987415 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 34890015 # DTB hits
-system.cpu.dtb.misses 97400 # DTB misses
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 88442007 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 88438073 # ITB hits
-system.cpu.itb.misses 3934 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 88442007 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 88438073 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 74756cd76..bec56725b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 9806a0cdd..621e65c84 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:32:07
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:03
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 66817a603..a690b2e36 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2514121 # Simulator instruction rate (inst/s)
-host_mem_usage 213276 # Number of bytes of host memory used
-host_seconds 35.14 # Real time elapsed on the host
-host_tick_rate 3846798027 # Simulator tick rate (ticks/s)
+host_inst_rate 2447162 # Simulator instruction rate (inst/s)
+host_mem_usage 215136 # Number of bytes of host memory used
+host_seconds 36.10 # Real time elapsed on the host
+host_tick_rate 3744340356 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4078.872537 # Cy
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
-system.cpu.dtb.accesses 34987415 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 34890015 # DTB hits
-system.cpu.dtb.misses 97400 # DTB misses
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs 88361638 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 88442008 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 88438074 # ITB hits
-system.cpu.itb.misses 3934 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 88442008 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 88438074 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 5b764e1f0..f0c5c3a9b 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.tracer]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 95b7d967f..9f2f0d730 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:53:28
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:31:45
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index be8f1d320..3f55620e8 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3821272 # Simulator instruction rate (inst/s)
-host_mem_usage 206688 # Number of bytes of host memory used
-host_seconds 35.63 # Real time elapsed on the host
-host_tick_rate 1912846403 # Simulator tick rate (ticks/s)
+host_inst_rate 3453262 # Simulator instruction rate (inst/s)
+host_mem_usage 208432 # Number of bytes of host memory used
+host_seconds 39.42 # Real time elapsed on the host
+host_tick_rate 1728626295 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 4e4bcb117..05ad8a083 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.l2cache]
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 397f2cd80..dcc6d4681 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:34
+M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 24dff0498..16a33a02d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1347607 # Simulator instruction rate (inst/s)
-host_mem_usage 214288 # Number of bytes of host memory used
-host_seconds 101.02 # Real time elapsed on the host
-host_tick_rate 2013168641 # Simulator tick rate (ticks/s)
+host_inst_rate 1887759 # Simulator instruction rate (inst/s)
+host_mem_usage 215972 # Number of bytes of host memory used
+host_seconds 72.12 # Real time elapsed on the host
+host_tick_rate 2820090693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.203377 # Number of seconds simulated