diff options
Diffstat (limited to 'tests/long/50.vortex')
23 files changed, 496 insertions, 677 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index cf4e15676..8c32bfa79 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -64,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -131,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -307,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -331,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -346,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -379,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -388,7 +346,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -403,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 52c225902..071b401c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,40 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3069385f0..bf6f402cd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13202034 # Number of BTB hits -global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups -global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted -global.BPredUnit.lookups 27047110 # Number of BP lookups -global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target. -host_inst_rate 69520 # Simulator instruction rate (inst/s) -host_mem_usage 239908 # Number of bytes of host memory used -host_seconds 1144.87 # Real time elapsed on the host -host_tick_rate 987535 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7411086 # Number of BTB hits +global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted +global.BPredUnit.lookups 14988034 # Number of BP lookups +global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target. +host_inst_rate 99683 # Simulator instruction rate (inst/s) +host_mem_usage 159476 # Number of bytes of host memory used +host_seconds 798.45 # Real time elapsed on the host +host_tick_rate 35303213 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.001131 # Number of seconds simulated -sim_ticks 1130602014 # Number of ticks simulated +sim_seconds 0.028188 # Number of seconds simulated +sim_ticks 28187684500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 89505192 +system.cpu.commit.COM:committed_per_cycle.samples 55590975 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 62882698 7025.59% - 1 8753972 978.04% - 2 5175203 578.20% - 3 3243621 362.39% - 4 2169519 242.39% - 5 1432847 160.09% - 6 1161882 129.81% - 7 791772 88.46% - 8 3893678 435.02% + 0 26501535 4767.24% + 1 10970497 1973.43% + 2 5466463 983.34% + 3 3506601 630.79% + 4 2372940 426.86% + 5 1558557 280.36% + 6 1098347 197.58% + 7 885461 159.28% + 8 3230574 581.13% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses +system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses -system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses +system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33325268 # number of overall hits -system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses -system.cpu.dcache.overall_misses 828340 # number of overall misses -system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33960866 # number of overall hits +system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses +system.cpu.dcache.overall_misses 702345 # number of overall misses +system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 201020 # number of replacements -system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200859 # number of replacements +system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use -system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147771 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched -system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use +system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147753 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched +system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 94208138 +system.cpu.fetch.rateDist.samples 56375518 system.cpu.fetch.rateDist.min_value 0 - 0 65459635 6948.41% - 1 1687117 179.08% - 2 1748812 185.63% - 3 1938924 205.81% - 4 6981531 741.08% - 5 6100701 647.58% - 6 758078 80.47% - 7 1979150 210.08% - 8 7554190 801.86% + 0 38672046 6859.72% + 1 1321940 234.49% + 2 1201428 213.11% + 3 1338454 237.42% + 4 3789980 672.27% + 5 1624217 288.11% + 6 592859 105.16% + 7 975150 172.97% + 8 6859444 1216.74% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency -system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses -system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency +system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses +system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 22631700 # number of overall hits -system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses -system.cpu.icache.overall_misses 101416 # number of overall misses -system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses +system.cpu.icache.overall_hits 12330467 # number of overall hits +system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses +system.cpu.icache.overall_misses 86010 # number of overall misses +system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85490 # number of replacements -system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks. +system.cpu.icache.replacements 82951 # number of replacements +system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use -system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use +system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14379719 # Number of branches executed -system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate -system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15338261 # Number of stores executed +system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14196900 # Number of branches executed +system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate +system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15052480 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value -system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back +system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value +system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34225955 # num instructions producing a value -system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle -system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 30345313 # num instructions producing a value +system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle +system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 49995908 53.38% # Type of FU issued - IntMult 43196 0.05% # Type of FU issued + IntAlu 45892607 55.70% # Type of FU issued + IntMult 44107 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 123595 0.13% # Type of FU issued - FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122386 0.13% # Type of FU issued - FloatMult 51 0.00% # Type of FU issued - FloatDiv 37853 0.04% # Type of FU issued + FloatAdd 116900 0.14% # Type of FU issued + FloatCmp 87 0.00% # Type of FU issued + FloatCvt 120453 0.15% # Type of FU issued + FloatMult 50 0.00% # Type of FU issued + FloatDiv 37768 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 27919833 29.81% # Type of FU issued - MemWrite 15421411 16.46% # Type of FU issued + MemRead 21065064 25.57% # Type of FU issued + MemWrite 15116696 18.35% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 83895 6.82% # attempts to use FU when none available + IntAlu 168043 18.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 589327 47.92% # attempts to use FU when none available - MemWrite 556570 45.26% # attempts to use FU when none available + MemRead 309725 34.49% # attempts to use FU when none available + MemWrite 420234 46.80% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138 +system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 54322746 5766.25% - 1 13333515 1415.33% - 2 10626230 1127.95% - 3 8813553 935.54% - 4 4440243 471.32% - 5 1597603 169.58% - 6 685526 72.77% - 7 334234 35.48% - 8 54488 5.78% + 0 22612550 4011.06% + 1 13769796 2442.51% + 2 7834961 1389.78% + 3 4029672 714.79% + 4 3712649 658.56% + 5 1993297 353.57% + 6 1449259 257.07% + 7 434309 77.04% + 8 539025 95.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate -system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate +system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 270292 # number of overall hits -system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170125 # number of overall misses +system.cpu.l2cache.overall_hits 267564 # number of overall hits +system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136892 # number of replacements -system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136843 # number of replacements +system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use -system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115938 # number of writebacks -system.cpu.numCycles 94208138 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use +system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115936 # number of writebacks +system.cpu.numCycles 56375518 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed -system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 179e8ea77..5339d79af 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -74,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 725aaed50..bf2c5c795 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 9c60e1316..16fb6367e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1347543 # Simulator instruction rate (inst/s) -host_mem_usage 179988 # Number of bytes of host memory used -host_seconds 65.56 # Real time elapsed on the host -host_tick_rate 1347535 # Simulator tick rate (ticks/s) +host_inst_rate 840697 # Simulator instruction rate (inst/s) +host_mem_usage 152968 # Number of bytes of host memory used +host_seconds 105.08 # Real time elapsed on the host +host_tick_rate 420346781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88340673 # Number of ticks simulated +sim_seconds 0.044170 # Number of seconds simulated +sim_ticks 44170336500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88340674 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0e1a3c9f1..4c8661842 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -62,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -101,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -140,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -173,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -182,11 +154,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -197,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 0dc85858d..c0cb264bc 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -64,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -101,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -139,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -177,25 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 9a9778162..107c46644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704446 # Simulator instruction rate (inst/s) -host_mem_usage 275648 # Number of bytes of host memory used -host_seconds 125.40 # Real time elapsed on the host -host_tick_rate 9716991 # Simulator tick rate (ticks/s) +host_inst_rate 585395 # Simulator instruction rate (inst/s) +host_mem_usage 158604 # Number of bytes of host memory used +host_seconds 150.91 # Real time elapsed on the host +host_tick_rate 839295251 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.001219 # Number of seconds simulated -sim_ticks 1218558003 # Number of ticks simulated +sim_seconds 0.126657 # Number of seconds simulated +sim_ticks 126656575000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.002965 # mi system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.numCycles 126656575000 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 7dbc37b58..da377104f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out index ee1fc877f..4d97fe26f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 323b8a93c..9dd2e7465 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 638506 # Simulator instruction rate (inst/s) -host_mem_usage 150340 # Number of bytes of host memory used -host_seconds 213.38 # Real time elapsed on the host -host_tick_rate 638505 # Simulator tick rate (ticks/s) +host_inst_rate 672762 # Simulator instruction rate (inst/s) +host_mem_usage 151516 # Number of bytes of host memory used +host_seconds 202.52 # Real time elapsed on the host +host_tick_rate 336380340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.000136 # Number of seconds simulated -sim_ticks 136246935 # Number of ticks simulated +sim_seconds 0.068123 # Number of seconds simulated +sim_ticks 68123467500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 136246936 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 8e5f7bf90..13addb638 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 21 2007 00:48:18 -M5 started Wed Mar 21 00:48:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:40:43 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 136246935 because target called exit() +Exiting @ tick 68123467500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 770dac1b9..ff1b40886 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out index 30db17922..c2fb507ae 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 78f34213e..bf74220de 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 473146 # Simulator instruction rate (inst/s) -host_mem_usage 156372 # Number of bytes of host memory used -host_seconds 287.96 # Real time elapsed on the host -host_tick_rate 4801122 # Simulator tick rate (ticks/s) +host_inst_rate 480067 # Simulator instruction rate (inst/s) +host_mem_usage 157016 # Number of bytes of host memory used +host_seconds 283.81 # Real time elapsed on the host +host_tick_rate 698858124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.001383 # Number of seconds simulated -sim_ticks 1382530003 # Number of ticks simulated +sim_seconds 0.198342 # Number of seconds simulated +sim_ticks 198341876000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_misses 150663 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses system.cpu.l2cache.overall_misses 135187 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 101911 # number of replacements system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 82918 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1382530003 # number of cpu cycles simulated +system.cpu.numCycles 198341876000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index dc2b61804..c635e0e4b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 03:55:17 -M5 started Thu Mar 29 03:55:38 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:44:06 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1382530003 because target called exit() +Exiting @ tick 198341876000 because target called exit() |