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-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini2
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr3
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout13
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt269
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini2
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr3
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout13
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt679
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr3
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/simple-timing/simout13
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt207
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/simple-timing/simout12
-rw-r--r--tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt207
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/50.vortex/ref/sparc/linux/simple-timing/simout14
-rw-r--r--tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt223
18 files changed, 849 insertions, 824 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 266b0ffd5..b77e3983a 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -186,7 +186,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr
index a263a334f..10a04a681 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr
@@ -4,3 +4,6 @@ warn: Prefetching currently unimplemented
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 14eb56bed..aa460e79e 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,11 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jun 25 2010 15:39:41
-M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
-M5 started Jun 25 2010 16:11:25
-M5 executing on zooks
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:06
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 104900991500 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index aeef950c2..0547798c7 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 46297 # Simulator instruction rate (inst/s)
-host_mem_usage 167032 # Number of bytes of host memory used
-host_seconds 1908.12 # Real time elapsed on the host
-host_tick_rate 55055354 # Simulator tick rate (ticks/s)
+host_inst_rate 31368 # Simulator instruction rate (inst/s)
+host_mem_usage 223704 # Number of bytes of host memory used
+host_seconds 2816.26 # Real time elapsed on the host
+host_tick_rate 37248320 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.105052 # Number of seconds simulated
-sim_ticks 105052358500 # Number of ticks simulated
+sim_seconds 0.104901 # Number of seconds simulated
+sim_ticks 104900991500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits
@@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 434959
system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 156428920 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 103882039 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 156429013 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 103882132 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 2136326 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 84.633296 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 2136233 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 84.755939 # Percentage of cycles cpu is active
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.comInts 30457224 # Number of Integer instructions committed
@@ -42,28 +42,28 @@ system.cpu.comStores 14844619 # Nu
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 2.378346 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.378346 # CPI: Total CPI of All Threads
+system.cpu.cpi 2.374919 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.374919 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38171.526841 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35064.773064 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2319531000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2312217500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2130746000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2123402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56426.999259 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53426.999259 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8452369500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8002990500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8303642500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7862076500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
@@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51158.585005 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10771900500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 51049.814620 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10615860000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10133736500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 9985478500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995308 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4076.781631 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.995330 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4076.871208 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51158.585005 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 51049.814620 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34679456 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10771900500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 210559 # number of overall misses
+system.cpu.dcache.overall_hits 34682064 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10615860000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 207951 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10133736500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 9985478500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.781631 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.871208 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 838762000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.dcache.warmup_cycle 834930000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 149164 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
@@ -126,14 +126,14 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19069.814885 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15852.089330 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 19062.290643 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96943862 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1514334000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1513736500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 79410 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1586 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1233673000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1233073000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@@ -145,31 +145,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19069.814885 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 19062.290643 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.demand_hits 96943862 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1514334000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1513736500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses
system.cpu.icache.demand_misses 79410 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1586 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1233673000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1233073000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.914669 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1873.241202 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.914717 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1873.340733 # Average occupied blocks per context
system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19069.814885 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 19062.290643 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 96943862 # number of overall hits
-system.cpu.icache.overall_miss_latency 1514334000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1513736500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses
system.cpu.icache.overall_misses 79410 # number of overall misses
system.cpu.icache.overall_mshr_hits 1586 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1233673000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1233073000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 75778 # number of replacements
system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1873.241202 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1873.340733 # Cycle average of tags in use
system.cpu.icache.total_refs 96943862 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 32286171 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.420460 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.420460 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 31982342 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.421067 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.421067 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@@ -201,104 +201,105 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.396941 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.233323 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7528713000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743153500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 7525926000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740992500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52301.497653 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.842643 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 95122 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2273441500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.313645 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 43468 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1738930500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313645 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 43468 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51889.300080 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 322492000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 95311 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2263590000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.312281 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43279 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1731370500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312281 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43279 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 186907000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144288500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.637249 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.646134 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52405.047421 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 95122 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9802154500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.662889 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 187046 # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 52405.560939 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 95365 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9789516000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.662028 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186803 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7482084000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.662889 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 187046 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 7472363000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.662028 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186803 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.083128 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.473986 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2723.922410 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15531.583322 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.089575 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.471967 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2935.193659 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15465.399858 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52405.047421 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52405.560939 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 95122 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9802154500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.662889 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 187046 # number of overall misses
+system.cpu.l2cache.overall_hits 95365 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9789516000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.662028 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186803 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7482084000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.662889 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 187046 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 7472363000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.662028 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186803 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 147731 # number of replacements
-system.cpu.l2cache.sampled_refs 172937 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147725 # number of replacements
+system.cpu.l2cache.sampled_refs 173054 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.505732 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 110204 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18400.593517 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 111816 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120636 # number of writebacks
-system.cpu.numCycles 210104718 # number of cpu cycles simulated
-system.cpu.runCycles 177818547 # Number of cycles cpu stages are processed.
+system.cpu.l2cache.writebacks 120606 # number of writebacks
+system.cpu.numCycles 209801984 # number of cpu cycles simulated
+system.cpu.runCycles 177819642 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 113077434 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 112774700 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 46.180440 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 121740642 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 88364076 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 42.057159 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 120288932 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization 46.247076 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 121437923 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 88364061 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 42.117839 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 119986198 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 42.748105 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 174873448 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization 42.809789 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 174570714 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 16.768434 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 121764045 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 16.792630 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 121461311 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 42.046021 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 210104718 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 42.106691 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 209801984 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 58500b489..0c3775172 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -353,7 +353,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
index b2d79346c..67f69f09d 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 409031e84..90ad95ec6 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,5 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,11 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:07:19
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:53:46
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 27109454000 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 7506a8fb6..aa0ed940f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 172331 # Simulator instruction rate (inst/s)
-host_mem_usage 216300 # Number of bytes of host memory used
-host_seconds 461.86 # Real time elapsed on the host
-host_tick_rate 58843672 # Simulator tick rate (ticks/s)
+host_inst_rate 111480 # Simulator instruction rate (inst/s)
+host_mem_usage 216720 # Number of bytes of host memory used
+host_seconds 713.95 # Real time elapsed on the host
+host_tick_rate 37970836 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.027177 # Number of seconds simulated
-sim_ticks 27177245500 # Number of ticks simulated
+sim_seconds 0.027109 # Number of seconds simulated
+sim_ticks 27109454000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 8069483 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 14149168 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 34397 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 454823 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 10566027 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 16273288 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1942431 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3319944 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 51827032 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 22597378 43.60% 43.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 11350095 21.90% 65.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 5102840 9.85% 75.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 3559000 6.87% 82.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2567186 4.95% 87.17% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 1515845 2.92% 90.09% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 1002832 1.93% 92.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 811912 1.57% 93.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 51827032 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 359545 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8408904 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.682916 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.682916 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 20447523 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30372.255855 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20950.835512 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20297704 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4550341000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007327 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 149819 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 88240 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1290131500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003012 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61579 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32253.546396 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35751.235092 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13562946 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 33880124994 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.071881 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1050431 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 900647 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 5354962997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149784 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3083 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 165.176300 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 18498 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 35060900 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32018.717762 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33860650 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 38430465994 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.034233 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1200250 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 988887 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6645094497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006028 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 211363 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995485 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4077.505020 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 35060900 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32018.717762 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33860650 # number of overall hits
-system.cpu.dcache.overall_miss_latency 38430465994 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.034233 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1200250 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 988887 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6645094497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006028 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 211363 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 33873274 # number of overall hits
+system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1196678 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 200975 # number of replacements
-system.cpu.dcache.sampled_refs 205071 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 200988 # number of replacements
+system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4077.505020 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33872869 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 182118000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147751 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3544786 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 96141 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3662025 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 101883380 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 28549595 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 19586782 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1306643 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 281833 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 145869 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 36634667 # DTB accesses
-system.cpu.dtb.data_acv 32 # DTB access violations
-system.cpu.dtb.data_hits 36459913 # DTB hits
-system.cpu.dtb.data_misses 174754 # DTB misses
+system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 149251 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 36643462 # DTB accesses
+system.cpu.dtb.data_acv 34 # DTB access violations
+system.cpu.dtb.data_hits 36467174 # DTB hits
+system.cpu.dtb.data_misses 176288 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 21560876 # DTB read accesses
-system.cpu.dtb.read_acv 29 # DTB read access violations
-system.cpu.dtb.read_hits 21402283 # DTB read hits
-system.cpu.dtb.read_misses 158593 # DTB read misses
-system.cpu.dtb.write_accesses 15073791 # DTB write accesses
-system.cpu.dtb.write_acv 3 # DTB write access violations
-system.cpu.dtb.write_hits 15057630 # DTB write hits
-system.cpu.dtb.write_misses 16161 # DTB write misses
-system.cpu.fetch.Branches 16273288 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13390069 # Number of cache lines fetched
-system.cpu.fetch.Cycles 33318554 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 152706 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 103441312 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 571617 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.299392 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 13390069 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 10011914 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.903087 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 53133675 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_accesses 21569273 # DTB read accesses
+system.cpu.dtb.read_acv 32 # DTB read access violations
+system.cpu.dtb.read_hits 21411172 # DTB read hits
+system.cpu.dtb.read_misses 158101 # DTB read misses
+system.cpu.dtb.write_accesses 15074189 # DTB write accesses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_hits 15056002 # DTB write hits
+system.cpu.dtb.write_misses 18187 # DTB write misses
+system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched
+system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53133675 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 13390069 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9552.030813 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6056.454886 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 13301016 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 850637000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.006651 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 89053 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 2816 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 522290500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.006440 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 86237 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 13386326 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 6054.988859 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 13297330 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.006648 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 88996 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 521770500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006437 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 86172 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 154.239714 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13390069 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9552.030813 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency
-system.cpu.icache.demand_hits 13301016 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 850637000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.006651 # miss rate for demand accesses
-system.cpu.icache.demand_misses 89053 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 2816 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 522290500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.006440 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 86237 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 9552.485505 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
+system.cpu.icache.demand_hits 13297330 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 850133000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.006648 # miss rate for demand accesses
+system.cpu.icache.demand_misses 88996 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 2824 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 521770500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.006437 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 86172 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.936831 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1918.630870 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 13390069 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9552.030813 # average overall miss latency
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+system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 13301016 # number of overall hits
-system.cpu.icache.overall_miss_latency 850637000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.006651 # miss rate for overall accesses
-system.cpu.icache.overall_misses 89053 # number of overall misses
-system.cpu.icache.overall_mshr_hits 2816 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 522290500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.006440 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 86237 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 84189 # number of replacements
-system.cpu.icache.sampled_refs 86236 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 84124 # number of replacements
+system.cpu.icache.sampled_refs 86171 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1918.630870 # Cycle average of tags in use
-system.cpu.icache.total_refs 13301016 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1918.688120 # Cycle average of tags in use
+system.cpu.icache.total_refs 13297330 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1220817 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14763362 # Number of branches executed
-system.cpu.iew.EXEC:nop 9403936 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.562245 # Inst execution rate
-system.cpu.iew.EXEC:refs 36977571 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15306943 # Number of stores executed
+system.cpu.idleCycles 1204946 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.iew.EXEC:rate 1.566510 # Inst execution rate
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 42200934 # num instructions consuming a value
-system.cpu.iew.WB:count 84440980 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.765693 # average fanout of values written-back
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+system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.765793 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 32312963 # num instructions producing a value
-system.cpu.iew.WB:rate 1.553523 # insts written-back per cycle
-system.cpu.iew.WB:sent 84676788 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 400577 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 625766 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 23022182 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 5008 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 344811 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16353481 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 99092373 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 21670628 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 531948 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 84915051 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 11175 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 32335073 # num instructions producing a value
+system.cpu.iew.WB:rate 1.557690 # insts written-back per cycle
+system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 401805 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 605778 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 23014883 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 5009 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 349401 # Number of squashed instructions skipped by dispatch
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+system.cpu.iew.iewDispatchedInsts 99082046 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 21679056 # Number of load instructions executed
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+system.cpu.iew.iewIQFullEvents 11054 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 9016 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1306643 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 43564 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 953335 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 730 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 953186 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 19282 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1358 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2642783 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1508862 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 19282 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 131988 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 268589 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.464309 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.464309 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 20710 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1355 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 2635484 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1503369 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 20710 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 131758 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 270047 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.467970 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 47956060 56.12% 56.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 42959 0.05% 56.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 47968991 56.12% 56.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 42906 0.05% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122263 0.14% 56.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122397 0.14% 56.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38515 0.05% 56.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 21777529 25.49% 81.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 15387138 18.01% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122147 0.14% 56.31% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122353 0.14% 56.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38520 0.05% 56.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 21790369 25.49% 82.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388261 18.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 85446999 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 982918 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011503 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 85473684 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 995540 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011647 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 100696 10.24% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 446429 45.42% 55.66% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 435793 44.34% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 102737 10.32% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.32% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 453943 45.60% 55.92% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 438860 44.08% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 53133675 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.608151 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.716289 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 53013963 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.612286 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.719350 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 17599811 33.12% 33.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 14135768 26.60% 59.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 8101815 15.25% 74.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 4767583 8.97% 83.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 4587960 8.63% 92.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 2114458 3.98% 96.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 1132800 2.13% 98.69% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 463918 0.87% 99.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 229562 0.43% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 17564950 33.13% 33.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 14012876 26.43% 59.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 8103290 15.29% 74.85% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 4796735 9.05% 83.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 4597424 8.67% 92.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 2085134 3.93% 96.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 1155738 2.18% 98.68% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 468299 0.88% 99.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 229517 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 53133675 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.572032 # Inst issue rate
-system.cpu.iq.iqInstsAdded 89683429 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 85446999 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 5008 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9879316 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 48902 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 6828439 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 53013963 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate
+system.cpu.iq.iqInstsAdded 89676572 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 85473684 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 5009 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 9869392 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 46778 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 13417164 # ITB accesses
+system.cpu.itb.fetch_accesses 13413339 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 13390069 # ITB hits
-system.cpu.itb.fetch_misses 27095 # ITB misses
+system.cpu.itb.fetch_hits 13386326 # ITB hits
+system.cpu.itb.fetch_misses 27013 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@@ -343,106 +343,107 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.441443 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.837093 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4926895499 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143493 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481550000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143493 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 147815 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34139.493240 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.309786 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 103139 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1525216000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.302243 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 44676 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1386533500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302243 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 44676 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6336 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34034.485480 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31031.960227 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 215642500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6336 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196618500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6336 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147751 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147751 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.679657 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 291308 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34288.918467 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 103139 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6452111499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.645945 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 188169 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5868083500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.645945 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 188169 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.090420 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.474090 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2962.888778 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15534.990261 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 291308 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34288.918467 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 103139 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6452111499 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.645945 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 188169 # number of overall misses
+system.cpu.l2cache.overall_hits 103332 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 187924 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5868083500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.645945 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 188169 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 148882 # number of replacements
-system.cpu.l2cache.sampled_refs 174101 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 148884 # number of replacements
+system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18497.879039 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 118329 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120652 # number of writebacks
-system.cpu.memDep0.conflictingLoads 12671277 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11281308 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 23022182 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16353481 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 54354492 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2040280 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 120621 # number of writebacks
+system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 54218909 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 60824 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 28947603 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1285549 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 34 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 121774399 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 101069730 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 60794101 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 19336245 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1306643 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1420628 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 8247220 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 82276 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 5281 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2797354 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 5278 # count of temporary serializing insts renamed
-system.cpu.timesIdled 42409 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed
+system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 436162c68..1aa6cf383 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
index b2d79346c..67f69f09d 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 5b5245d37..a83443919 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,11 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:21:01
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:57:42
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 135015129000 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 3f747beae..e11ad72a2 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1182325 # Simulator instruction rate (inst/s)
-host_mem_usage 200332 # Number of bytes of host memory used
-host_seconds 74.72 # Real time elapsed on the host
-host_tick_rate 1809050434 # Simulator tick rate (ticks/s)
+host_inst_rate 1159310 # Simulator instruction rate (inst/s)
+host_mem_usage 215356 # Number of bytes of host memory used
+host_seconds 76.20 # Real time elapsed on the host
+host_tick_rate 1771821789 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.135169 # Number of seconds simulated
-sim_ticks 135168766000 # Number of ticks simulated
+sim_seconds 0.135015 # Number of seconds simulated
+sim_ticks 135015129000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2294180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2111882000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8240064000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7798509000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 50657.337546 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10534244000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 9910391000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995818 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4078.872537 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.995838 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4078.950714 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50657.337546 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34679456 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 210559 # number of overall misses
+system.cpu.dcache.overall_hits 34682064 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10534244000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 207951 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 9910391000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4078.950714 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.dcache.warmup_cycle 943578000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 149164 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
@@ -90,13 +90,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 18802.449108 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15802.449108 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1437184000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1207876000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@@ -108,31 +108,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 18802.449108 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1437184000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1207876000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.913950 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1871.768668 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.913991 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1871.853872 # Average occupied blocks per context
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 18802.449108 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88361638 # number of overall hits
-system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1437184000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1207876000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1871.853872 # Cycle average of tags in use
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 7463248000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740960000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 94094 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2241616000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.314194 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43108 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1724320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314194 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43108 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51596.340449 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 186108000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.639727 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 94148 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9704864000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.664691 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186632 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 7465280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.664691 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186632 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.081795 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.475328 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2680.267907 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15575.557767 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.088307 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.473299 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2893.659899 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15509.045444 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 93905 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 186875 # number of overall misses
+system.cpu.l2cache.overall_hits 94148 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9704864000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.664691 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186632 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 7465280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.664691 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186632 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 147561 # number of replacements
-system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147555 # number of replacements
+system.cpu.l2cache.sampled_refs 172883 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18402.705343 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 110598 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120634 # number of writebacks
+system.cpu.l2cache.writebacks 120604 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 270337532 # number of cpu cycles simulated
+system.cpu.numCycles 270030258 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index c968b9735..2a754cafb 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -152,7 +152,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 7aba6f5e0..92e232392 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,12 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:39:36
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:53:04
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 133556162000 because target called exit()
+Exiting @ tick 133464153000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b085aeacb..0ce9c5c87 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1745846 # Simulator instruction rate (inst/s)
-host_mem_usage 217668 # Number of bytes of host memory used
-host_seconds 56.13 # Real time elapsed on the host
-host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
+host_inst_rate 1245224 # Simulator instruction rate (inst/s)
+host_mem_usage 218772 # Number of bytes of host memory used
+host_seconds 78.70 # Real time elapsed on the host
+host_tick_rate 1695886374 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
-sim_seconds 0.133556 # Number of seconds simulated
-sim_ticks 133556162000 # Number of ticks simulated
+sim_seconds 0.133464 # Number of seconds simulated
+sim_ticks 133464153000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35927.990796 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32927.990796 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 35865.411818 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32865.411818 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1904938000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1901620000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 53021 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1745875000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1742557000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 53021 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.910387 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.910387 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 19754229 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6249086000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005617 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 111591 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5914313000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005617 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 111591 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55969.020638 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52969.020638 # average WriteReq mshr miss latency
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+system.cpu.dcache.WriteReq_mshr_misses 110041 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 292.838112 # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 47030259 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 49534.809127 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
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-system.cpu.dcache.demand_miss_latency 8154024000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003500 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 164612 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 49432.160773 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7660188000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003500 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 164612 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995356 # Average percentage of cache occupancy
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+system.cpu.dcache.occ_%::0 0.995361 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 47030259 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 49534.809127 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 46534.809127 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 49432.160773 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 46865647 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8154024000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003500 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 164612 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7660188000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003500 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 164612 # number of overall MSHR misses
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+system.cpu.dcache.overall_mshr_misses 163062 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 155959 # number of replacements
system.cpu.dcache.sampled_refs 160055 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.978068 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.997954 # Cycle average of tags in use
system.cpu.dcache.total_refs 46870204 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1080546000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 109433 # number of writebacks
+system.cpu.dcache.warmup_cycle 1079446000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 110614 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 78097320 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24226.782314 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21226.782314 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24224.561032 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21224.561032 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 78078412 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 458080000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 458038000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 401356000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 401314000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 78097320 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24226.782314 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24224.561032 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
system.cpu.icache.demand_hits 78078412 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 458080000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 401356000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.847875 # Average percentage of cache occupancy
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+system.cpu.icache.occ_%::0 0.847896 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 78097320 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24226.782314 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21226.782314 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24224.561032 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 78078412 # number of overall hits
-system.cpu.icache.overall_miss_latency 458080000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 458038000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_misses 18908 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 401356000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 401314000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 16890 # number of replacements
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1736.448416 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1736.491216 # Cycle average of tags in use
system.cpu.icache.total_refs 78078412 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4281360000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadReq_accesses 71929 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadReq_mshr_misses 32286 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 4557 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 236444000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 156000000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_misses 3007 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 4557 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 109433 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 109433 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.l2cache.avg_refs 0.368048 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 178963 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.overall_accesses 178963 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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-system.cpu.l2cache.total_refs 47564 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 17940.103104 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 48901 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 88579 # number of writebacks
+system.cpu.l2cache.writebacks 88549 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 267112324 # number of cpu cycles simulated
+system.cpu.numCycles 266928306 # number of cpu cycles simulated
system.cpu.num_insts 97997303 # Number of instructions executed
system.cpu.num_refs 47871034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 8638f5771..c85b36dc7 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index 0431d5fd8..b0fb854c0 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,12 +7,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:34:57
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:06:02
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 203376692000 because target called exit()
+Exiting @ tick 203281649000 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index fe7329cf3..ca8b32bef 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 755710 # Simulator instruction rate (inst/s)
-host_mem_usage 202292 # Number of bytes of host memory used
-host_seconds 180.15 # Real time elapsed on the host
-host_tick_rate 1128944281 # Simulator tick rate (ticks/s)
+host_inst_rate 1039608 # Simulator instruction rate (inst/s)
+host_mem_usage 220432 # Number of bytes of host memory used
+host_seconds 130.95 # Real time elapsed on the host
+host_tick_rate 1552328099 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
-sim_seconds 0.203377 # Number of seconds simulated
-sim_ticks 203376692000 # Number of ticks simulated
+sim_seconds 0.203282 # Number of seconds simulated
+sim_ticks 203281649000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38539.616255 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35539.616255 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1753514000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1617017000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_hits 15879 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 2072000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.002325 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 37 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 1961000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.002325 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 37 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55967.131927 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52967.131927 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 20756479 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6034656000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.005168 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 107825 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5711181000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005168 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 107825 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
@@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 50795.504944 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 57942281 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7788170000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002639 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 153324 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7328198000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002639 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 153324 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997952 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4087.609698 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.997956 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4087.629454 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50795.504944 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 57940701 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 154904 # number of overall misses
+system.cpu.dcache.overall_hits 57942281 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7788170000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002639 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 153324 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7328198000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002639 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 153324 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4087.629454 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 107279 # number of writebacks
+system.cpu.dcache.warmup_cycle 776960000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 108328 # number of writebacks
system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16931.987339 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13931.987339 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 3166688000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 2605616000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 16931.987339 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 3166688000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 2605616000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.978865 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 2004.715107 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.978873 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 2004.731937 # Average occupied blocks per context
system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16931.987339 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 134366560 # number of overall hits
-system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 3166688000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 2605616000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -134,44 +134,45 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 2004.731937 # Cycle average of tags in use
system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle 144738462000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 84 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 5464940000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999201 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 105095 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4203800000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999201 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 105095 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 192883 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2061280000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.170478 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 39640 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1585600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170478 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 39640 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 2683 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51689.899366 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 138684000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 2683 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 107320000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 107279 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 2683 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 108328 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 108328 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.433874 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.441131 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 192967 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 7526220000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.428588 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 144735 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 5789400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.428588 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 144735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.120206 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.469380 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3938.922202 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15380.640176 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.127128 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.467489 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 4165.731733 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15318.691405 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 192777 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 144925 # number of overall misses
+system.cpu.l2cache.overall_hits 192967 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 7526220000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.428588 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 144735 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 5789400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.428588 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 144735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 120487 # number of replacements
-system.cpu.l2cache.sampled_refs 139197 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 120481 # number of replacements
+system.cpu.l2cache.sampled_refs 139283 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 19319.562378 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 199591 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 19484.423138 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 200725 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 87414 # number of writebacks
+system.cpu.l2cache.writebacks 87388 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 406753384 # number of cpu cycles simulated
+system.cpu.numCycles 406563298 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls