summaryrefslogtreecommitdiff
path: root/tests/long/50.vortex
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/50.vortex')
-rwxr-xr-xtests/long/50.vortex/ref/alpha/tru64/o3-timing/simout4
-rw-r--r--tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt28
-rwxr-xr-xtests/long/50.vortex/ref/arm/linux/o3-timing/simout4
-rw-r--r--tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt28
4 files changed, 32 insertions, 32 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 0e04160b4..2d55160c7 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 19 2011 11:52:53
-M5 started Apr 19 2011 11:58:35
+M5 compiled Apr 21 2011 12:29:56
+M5 started Apr 21 2011 13:02:51
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 2aed2a2e0..713ba31b4 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 329538 # Simulator instruction rate (inst/s)
-host_mem_usage 213968 # Number of bytes of host memory used
-host_seconds 241.53 # Real time elapsed on the host
-host_tick_rate 105857368 # Simulator tick rate (ticks/s)
+host_inst_rate 200493 # Simulator instruction rate (inst/s)
+host_mem_usage 217108 # Number of bytes of host memory used
+host_seconds 396.98 # Real time elapsed on the host
+host_tick_rate 64404396 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.025567 # Number of seconds simulated
@@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu
system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 1016178 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 6217 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1472 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2214794 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1168217 # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 8381f7581..f3dc52cc8 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 13:18:26
+M5 compiled Apr 21 2011 12:05:01
+M5 started Apr 21 2011 14:53:22
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 50e06cc2a..d0dfce1d1 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 252526 # Simulator instruction rate (inst/s)
-host_mem_usage 223792 # Number of bytes of host memory used
-host_seconds 398.51 # Real time elapsed on the host
-host_tick_rate 100102950 # Simulator tick rate (ticks/s)
+host_inst_rate 153606 # Simulator instruction rate (inst/s)
+host_mem_usage 226292 # Number of bytes of host memory used
+host_seconds 655.14 # Real time elapsed on the host
+host_tick_rate 60890397 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 100633305 # Number of instructions simulated
sim_seconds 0.039892 # Number of seconds simulated
@@ -270,16 +270,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu
system.cpu.iew.iewLSQFullEvents 6915 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2130394 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 55938 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 1108085 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 8523 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 41 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2436412 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1650781 # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads 1108085 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation 8523 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads 2436412 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores 1650781 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly