diff options
Diffstat (limited to 'tests/long/50.vortex')
| -rwxr-xr-x | tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 148 |
2 files changed, 77 insertions, 77 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index bbbd6fcec..84d8d4369 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:09:12 +M5 compiled Jul 6 2009 11:03:45 +M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip +M5 started Jul 6 2009 11:55:23 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f8c066dab..254fb17d5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 261277 # Simulator instruction rate (inst/s) -host_mem_usage 216964 # Number of bytes of host memory used -host_seconds 304.63 # Real time elapsed on the host -host_tick_rate 89075669 # Simulator tick rate (ticks/s) +host_inst_rate 254468 # Simulator instruction rate (inst/s) +host_mem_usage 199708 # Number of bytes of host memory used +host_seconds 312.78 # Real time elapsed on the host +host_tick_rate 86754409 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated @@ -20,22 +20,22 @@ system.cpu.commit.COM:branches 13754477 # Nu system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle::samples 51751169 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 22506446 43.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 11357579 21.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5114502 9.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3560855 6.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2552504 4.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1532717 2.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 1008933 1.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 796739 1.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3320894 6.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 51751169 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 1.707028 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.326549 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 22506446 43.49% 43.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 11357579 21.95% 65.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5114502 9.88% 75.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3560855 6.88% 82.20% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2552504 4.93% 87.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1532717 2.96% 90.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 1008933 1.95% 92.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 796739 1.54% 93.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3320894 6.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51751169 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -152,22 +152,22 @@ system.cpu.fetch.icacheStallCycles 13386072 # Nu system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 33206277 62.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1871594 3.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1529415 2.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1809626 3.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 3985239 7.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1867239 3.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 695846 1.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1111736 2.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6964298 13.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.947692 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.940902 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 33206277 62.60% 62.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1871594 3.53% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1529415 2.88% 69.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1809626 3.41% 72.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 3985239 7.51% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1867239 3.52% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 695846 1.31% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1111736 2.10% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6964298 13.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 53041270 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency @@ -267,54 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 106828 # N system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47898565 56.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 42953 0.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 121655 0.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 88 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122104 0.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 53 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38535 0.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21753622 25.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15368770 18.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 47898565 56.12% 56.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42953 0.05% 56.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 121655 0.14% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 88 0.00% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122104 0.14% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 53 0.00% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38535 0.05% 56.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21753622 25.49% 81.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15368770 18.01% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::total 85346345 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 97100 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 470602 48.04% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 411938 42.05% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97100 9.91% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 470602 48.04% 57.95% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 411938 42.05% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% 33.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% 59.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% 74.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% 84.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% 92.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% 96.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% 98.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% 99.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued |