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-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini28
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out105
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt2167
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout27
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout27
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt2048
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout27
15 files changed, 701 insertions, 6904 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..7a3bd9383 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -102,14 +100,15 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
+progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
@@ -131,7 +130,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -308,7 +306,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +345,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +418,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
index f491a3081..1077b5dd7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
@@ -19,54 +19,25 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
@@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
+progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
@@ -283,7 +255,44 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +331,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -354,10 +362,14 @@ hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +408,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..73d6efd18 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
+global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
+global.BPredUnit.lookups 1098978166 # Number of BP lookups
+global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
+host_inst_rate 27542 # Simulator instruction rate (inst/s)
+host_mem_usage 1254844 # Number of bytes of host memory used
+host_seconds 63032.08 # Real time elapsed on the host
+host_tick_rate 395232 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+sim_insts 1736043781 # Number of instructions simulated
+sim_seconds 0.024912 # Number of seconds simulated
+sim_ticks 24912272090 # Number of ticks simulated
+system.cpu.commit.COM:branches 214632552 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.samples 5678957793
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
+ 0 5103057521 8985.90%
+ 1 193842571 341.33%
+ 2 126727829 223.15%
+ 3 63255233 111.39%
+ 4 47590442 83.80%
+ 5 34302037 60.40%
+ 6 22774532 40.10%
+ 7 15063971 26.53%
+ 8 72343657 127.39%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:count 1819780126 # Number of instructions committed
+system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
+system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 611672543 # number of overall hits
+system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 15232438 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9173157 # number of replacements
+system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
+system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244715 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.samples 6180887586
system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
+ 0 4766540797 7711.74%
+ 1 80764415 130.67%
+ 2 63598055 102.89%
+ 3 58203597 94.17%
+ 4 424384465 686.61%
+ 5 69131012 111.85%
+ 6 94422767 152.77%
+ 7 44649271 72.24%
+ 8 579193207 937.07%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
+system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 541279194 # number of overall hits
+system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1290 # number of overall misses
+system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
+system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
+system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
+system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
+system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
+system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
+system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 11190791 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 10765863 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 1970711875 65.43% # Type of FU issued
+ IntMult 679 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
+ FloatAdd 206 0.00% # Type of FU issued
+ FloatCmp 15 0.00% # Type of FU issued
+ FloatCvt 146 0.00% # Type of FU issued
+ FloatMult 12 0.00% # Type of FU issued
+ FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
+ MemRead 862446019 28.64% # Type of FU issued
+ MemWrite 178606255 5.93% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
+ IntAlu 509990 4.51% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -1863,78 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
+ MemRead 9173598 81.13% # attempts to use FU when none available
+ MemWrite 1623963 14.36% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
+ 0 4878979324 7893.65%
+ 1 360055339 582.53%
+ 2 481197713 778.53%
+ 3 280796976 454.30%
+ 4 94854448 153.46%
+ 5 50760526 82.12%
+ 6 26723872 43.24%
+ 7 6795220 10.99%
+ 8 724168 1.17%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244715 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215400 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.013060 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29315 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.013060 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29315 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 9224389 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2198480 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2136397 # number of replacements
+system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1039341 # number of writebacks
+system.cpu.numCycles 6180887586 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
+system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..ad57a5293 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
index f491a3081..891519c26 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..7422e3ae7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 927424 # Simulator instruction rate (inst/s)
+host_mem_usage 144704 # Number of bytes of host memory used
+host_seconds 1962.19 # Real time elapsed on the host
+host_tick_rate 927424 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
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- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.001820 # Number of seconds simulated
+sim_ticks 1819780128 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1819780129 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..0a123d4a4 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
index f491a3081..4692c5d40 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..45b7beb7c 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 486900 # Simulator instruction rate (inst/s)
+host_mem_usage 1198232 # Number of bytes of host memory used
+host_seconds 3737.50 # Real time elapsed on the host
+host_tick_rate 8500130 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.031769 # Number of seconds simulated
+sim_ticks 31769223012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 596212431 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1819779328 # number of overall hits
+system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
+system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
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-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
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- 30 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
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- 30 0
- 32 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 50 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 48 0
- 50 0
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- 62 0
- 64 0
- 66 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
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- 62 0
- 64 0
- 66 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 50 0
- 52 0
- 54 0
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- 64 0
- 66 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 30 0
- 32 0
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- 40 0
- 42 0
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- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
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- 50 0
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- 74 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
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- 22 0
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- 76 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 9167994 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2189250 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2127385 # number of replacements
+system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1038202 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 31769223012 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!