diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 561 |
1 files changed, 282 insertions, 279 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 3b06d5b45..a608e7e97 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,301 +1,304 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 191712 # Simulator instruction rate (inst/s) -host_mem_usage 1122860 # Number of bytes of host memory used -host_seconds 9492.28 # Real time elapsed on the host -host_tick_rate 103236678 # Simulator tick rate (ticks/s) +sim_seconds 1.016489 # Number of seconds simulated +sim_ticks 1016488689500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 111625 # Simulator instruction rate (inst/s) +host_tick_rate 62351436 # Simulator tick rate (ticks/s) +host_mem_usage 193064 # Number of bytes of host memory used +host_seconds 16302.57 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated -sim_seconds 0.979951 # Number of seconds simulated -sim_ticks 979951369500 # Number of ticks simulated -system.cpu.activity 74.309805 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 614316005 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 69.872947 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 82064192 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 117447733 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 79224651 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 175157411 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 253574750 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. -system.cpu.comBranches 214632552 # Number of Branches instructions committed -system.cpu.comFloats 190 # Number of Floating Point instructions committed -system.cpu.comInts 916086844 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 444614416 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449511494 # DTB read accesses +system.cpu.dtb.write_hits 160920901 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162622205 # DTB write accesses +system.cpu.dtb.data_hits 605535317 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 612133699 # DTB accesses +system.cpu.itb.fetch_hits 237932826 # ITB hits +system.cpu.itb.fetch_misses 22 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 237932848 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 2032977380 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 1759886457 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 7533536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 440243372 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1592734008 # Number of cycles cpu stages are processed. +system.cpu.activity 78.344896 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed -system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed -system.cpu.comNops 83736345 # Number of Nop instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed +system.cpu.comBranches 214632552 # Number of Branches instructions committed +system.cpu.comNops 83736345 # Number of Nop instructions committed +system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed +system.cpu.comInts 916086844 # Number of Integer instructions committed +system.cpu.comFloats 190 # Number of Floating Point instructions committed system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 1.077000 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 1.077000 # CPI: Total CPI of All Threads +system.cpu.cpi 1.117156 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 1.117156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.895131 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.895131 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 338882102 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 262365824 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 145832523 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 223761389 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 153206045 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 68.468490 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 189687399 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 149194703 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667621622 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3043824239 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 226 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 571 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 655476684 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617179738 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 132311663 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 6922402 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 139234065 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 75965071 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 64.700104 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1137833135 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 823371490 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1209605890 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.499230 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1094712452 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 938264928 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.152256 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1056818268 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 976159112 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.016231 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1623201304 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409776076 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.156450 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1008711848 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1024265532 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.382535 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.tagsinuse 664.417711 # Cycle average of tags in use +system.cpu.icache.total_refs 237931761 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 277309.744755 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 664.417711 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324423 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 237931761 # number of ReadReq hits +system.cpu.icache.demand_hits 237931761 # number of demand (read+write) hits +system.cpu.icache.overall_hits 237931761 # number of overall hits +system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses +system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 58372500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 58372500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 58372500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 237932823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 237932823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 237932823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54964.689266 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 81000 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 45874500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45874500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45874500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53466.783217 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9107352 # number of replacements +system.cpu.dcache.tagsinuse 4082.698985 # Cycle average of tags in use +system.cpu.dcache.total_refs 595070238 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310172 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12613555000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4082.698985 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996753 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 437271427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 157798811 # number of WriteReq hits +system.cpu.dcache.demand_hits 595070238 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 595070238 # number of overall hits +system.cpu.dcache.ReadReq_misses 7324236 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 2929691 # number of WriteReq misses +system.cpu.dcache.demand_misses 10253927 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 10253927 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 180890019000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110280256500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 291170275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 291170275500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24782.275660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21696.910468 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 437273551 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 181458598000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016469 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7322112 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 99789 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 156702095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222323 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 36133.458705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30848.973440 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158603354 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76788947500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013222 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2125148 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235828 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 58283582500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15086.569579 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 65.397306 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 618 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9323500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27335.708502 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595876905 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 258247545500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9447260 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 335617 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 214985678000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9111643 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4081.685602 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27335.708502 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595876905 # number of overall hits -system.cpu.dcache.overall_miss_latency 258247545500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9447260 # number of overall misses -system.cpu.dcache.overall_mshr_hits 335617 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 214985678000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9111643 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.018228 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 24697.459093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37642.282582 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 28395.977024 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 28395.977024 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10999500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8090380500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208980 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.882651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38713.659202 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 3058572 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 101954 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1040525 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1142479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1142479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9107547 # number of replacements -system.cpu.dcache.sampled_refs 9111643 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 156087353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 59191861000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215279214000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215279214000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.916151 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.270960 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4081.685602 # Cycle average of tags in use -system.cpu.dcache.total_refs 595876905 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12696089000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3058780 # number of writebacks -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.execution_unit.executions 1162207758 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 135407901 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 207004701 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 54777.453839 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 207003672 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 56366000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1029 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 169 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23666.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 240701.944186 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 142000 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 207004701 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 54777.453839 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency -system.cpu.icache.demand_hits 207003672 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 56366000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_misses 1029 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 169 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 860 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 664.403935 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324416 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 207004701 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 54777.453839 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 207003672 # number of overall hits -system.cpu.icache.overall_miss_latency 56366000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_misses 1029 # number of overall misses -system.cpu.icache.overall_mshr_hits 169 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 860 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 860 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 664.403935 # Cycle average of tags in use -system.cpu.icache.total_refs 207003672 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 503502831 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.928505 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.928505 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 207004724 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 207004706 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52171.425069 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.113019 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 1000086 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 46392605000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.470664 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 889234 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569460500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 889234 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223183 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52232.293721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40052.296896 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5415265 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94431704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.250294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1807918 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72411268500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1807918 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 3058780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3058780 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.790606 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2686299 # number of replacements +system.cpu.l2cache.tagsinuse 26362.253179 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 225759748000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15507.582634 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10854.670545 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.473254 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.331258 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6415150 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2697156 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 94453448000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 46507349000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 140960797000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 140960797000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9112306 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52245.390045 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.050659 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9112503 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52212.225711 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6415351 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 140824309000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.295984 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2697152 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1170911 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 107980729000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.295984 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2697152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15023.339345 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11052.003329 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.458476 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.337280 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9112503 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52212.225711 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6415351 # number of overall hits -system.cpu.l2cache.overall_miss_latency 140824309000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.295984 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2697152 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 107980729000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.295984 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2697152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2686322 # number of replacements -system.cpu.l2cache.sampled_refs 2710967 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 72354306000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671086000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 108025392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108025392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.608723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.547862 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26075.342674 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7565242 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 230207194000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1170923 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed -system.cpu.numCycles 1959902740 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 1801820745 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 1376202963 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 1456399909 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 902142172 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 895662206 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 923587455 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 422410393 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 932643705 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 1619523667 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 8517352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |