diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d858d0b22..411912baf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254978 # Simulator instruction rate (inst/s) -host_mem_usage 190768 # Number of bytes of host memory used -host_seconds 6808.60 # Real time elapsed on the host -host_tick_rate 109025257 # Simulator tick rate (ticks/s) +host_inst_rate 176404 # Simulator instruction rate (inst/s) +host_mem_usage 192532 # Number of bytes of host memory used +host_seconds 9841.32 # Real time elapsed on the host +host_tick_rate 75427820 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -103,6 +103,10 @@ system.cpu.dcache.demand_mshr_misses 9523666 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.997499 # Average percentage of cache occupancy +system.cpu.dcache.occ_%::1 -0.003145 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4085.757368 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -12.883149 # Average occupied blocks per context system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency @@ -209,6 +213,8 @@ system.cpu.icache.demand_mshr_misses 902 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.347376 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 711.425375 # Average occupied blocks per context system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency @@ -399,6 +405,10 @@ system.cpu.l2cache.demand_mshr_misses 3773319 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.453663 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.336804 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 14865.634361 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11036.400552 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency |