diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt | 62 |
1 files changed, 39 insertions, 23 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 6f7531c90..a6eb50453 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1593285 # Simulator instruction rate (inst/s) -host_mem_usage 199472 # Number of bytes of host memory used -host_seconds 1142.16 # Real time elapsed on the host -host_tick_rate 2268225007 # Simulator tick rate (ticks/s) +host_inst_rate 1514723 # Simulator instruction rate (inst/s) +host_mem_usage 181532 # Number of bytes of host memory used +host_seconds 1201.39 # Real time elapsed on the host +host_tick_rate 2161875158 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1819780129 # Number of instructions simulated -sim_seconds 2.590667 # Number of seconds simulated -sim_ticks 2590666806000 # Number of ticks simulated +sim_insts 1819780127 # Number of instructions simulated +sim_seconds 2.597265 # Number of seconds simulated +sim_ticks 2597265186000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.283777 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.325443 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40727264000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40727877000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks -system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 611922547 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 605324165 # DTB hits +system.cpu.dtb.misses 6598382 # DTB misses +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1819779328 # number of overall hits +system.cpu.icache.overall_hits 1826377708 # number of overall hits system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.417495 # Cycle average of tags in use -system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 611.506832 # Cycle average of tags in use +system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 1826378528 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1826378510 # ITB hits +system.cpu.itb.misses 18 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1367767 # number of replacements system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18546.386002 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18552.565433 # Cycle average of tags in use system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2030116907000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2590666806000 # number of cpu cycles simulated -system.cpu.num_insts 1819780129 # Number of instructions executed -system.cpu.num_refs 606571345 # Number of memory references +system.cpu.numCycles 2597265186000 # number of cpu cycles simulated +system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- |