diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt | 109 |
1 files changed, 53 insertions, 56 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index afbd9c385..c79bac28f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1279505 # Simulator instruction rate (inst/s) -host_mem_usage 199716 # Number of bytes of host memory used -host_seconds 1422.25 # Real time elapsed on the host -host_tick_rate 1826162604 # Simulator tick rate (ticks/s) +host_inst_rate 890836 # Simulator instruction rate (inst/s) +host_mem_usage 328448 # Number of bytes of host memory used +host_seconds 2042.78 # Real time elapsed on the host +host_tick_rate 1270245606 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.597265 # Number of seconds simulated -sim_ticks 2597265186000 # Number of ticks simulated +sim_seconds 2.594831 # Number of seconds simulated +sim_ticks 2594830590000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 16114.256812 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14114.256812 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 118818430000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 116383834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 104373602000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 101939006000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18480.410584 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 18223.331337 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 175013480000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 172578884000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 156073048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 153638452000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18480.410584 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 18223.331337 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 175013480000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 172578884000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470216 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 156073048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 153638452000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.325443 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.310460 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40727877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40726989000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dtb.accesses 611922547 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.506832 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.506560 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # nu system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5145160 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 45717232000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.287691 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2078056 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 22858616000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2078056 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 41253806000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.018082 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21978.336430 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 7886252000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 7878838000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 2244708 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 2244708 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.187898 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5145160 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 87282272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.435376 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3967376 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 82818846000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 43641136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.435376 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3967376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 41409423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 9112536 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5145160 # number of overall hits -system.cpu.l2cache.overall_miss_latency 87282272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.435376 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3967376 # number of overall misses +system.cpu.l2cache.overall_hits 5348043 # number of overall hits +system.cpu.l2cache.overall_miss_latency 82818846000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3764493 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 43641136000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.435376 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3967376 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 41409423000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1367767 # number of replacements -system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2751986 # number of replacements +system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18552.565433 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.tagsinuse 25384.669947 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 571912424000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1194738 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5194530372 # number of cpu cycles simulated +system.cpu.numCycles 5189661180 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls |