diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 250 |
1 files changed, 250 insertions, 0 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt new file mode 100644 index 000000000..027e53548 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,250 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1294592 # Simulator instruction rate (inst/s) +host_mem_usage 201124 # Number of bytes of host memory used +host_seconds 1405.68 # Real time elapsed on the host +host_tick_rate 1940692275 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1819780127 # Number of instructions simulated +sim_seconds 2.727991 # Number of seconds simulated +sim_ticks 2727990505000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 595853949 # number of overall hits +system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9470216 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 9107638 # number of replacements +system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use +system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244708 # number of writebacks +system.cpu.dtb.accesses 611922547 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 605324165 # DTB hits +system.cpu.dtb.misses 6598382 # DTB misses +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 802 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1826377708 # number of overall hits +system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 802 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use +system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 1826378528 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1826378510 # ITB hits +system.cpu.itb.misses 18 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5348043 # number of overall hits +system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3764493 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 2751986 # number of replacements +system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1194738 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5455981010 # number of cpu cycles simulated +system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.num_refs 613169725 # Number of memory references +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls + +---------- End Simulation Statistics ---------- |