diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 185 |
1 files changed, 93 insertions, 92 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index a48cc62c7..713e89734 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1190978 # Simulator instruction rate (inst/s) -host_mem_usage 191664 # Number of bytes of host memory used -host_seconds 1527.97 # Real time elapsed on the host -host_tick_rate 1785366772 # Simulator tick rate (ticks/s) +host_inst_rate 1235575 # Simulator instruction rate (inst/s) +host_mem_usage 206704 # Number of bytes of host memory used +host_seconds 1472.82 # Real time elapsed on the host +host_tick_rate 1836801554 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.727991 # Number of seconds simulated -sim_ticks 2727990505000 # Number of ticks simulated +sim_seconds 2.705279 # Number of seconds simulated +sim_ticks 2705279137000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency +system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.996068 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4079.892573 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470216 # number of overall misses +system.cpu.dcache.overall_hits 596101072 # number of overall hits +system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9223093 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244708 # number of writebacks +system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2365949 # number of writebacks system.cpu.dtb.data_accesses 611922547 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 605324165 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.298700 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 611.737435 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.515193 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5565183 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 184462356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.389283 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3547353 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 141894120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3547353 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.438454 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.335641 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 14367.257286 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10998.286802 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.466649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.320836 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15291.153152 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5348043 # number of overall hits -system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3764493 # number of overall misses +system.cpu.l2cache.overall_hits 5565183 # number of overall hits +system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.389283 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3547353 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3547353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2751986 # number of replacements -system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2701645 # number of replacements +system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1194738 # number of writebacks +system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1175830 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5455981010 # number of cpu cycles simulated +system.cpu.numCycles 5410558274 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls |