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-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini9
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt8
3 files changed, 11 insertions, 14 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index f8a290050..fd5428b3a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
-mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
-mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
-mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index a3ccdd7b3..3314840b7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr 8 2009 12:43:13
-M5 executing on maize
+M5 compiled Apr 21 2009 16:38:39
+M5 revision e6dd09514462 6117 default qtip tip stats-update
+M5 started Apr 21 2009 16:41:08
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 6127ea9b9..5f4f3edad 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2385042 # Simulator instruction rate (inst/s)
-host_mem_usage 204904 # Number of bytes of host memory used
-host_seconds 763.00 # Real time elapsed on the host
-host_tick_rate 3575360927 # Simulator tick rate (ticks/s)
+host_inst_rate 1697488 # Simulator instruction rate (inst/s)
+host_mem_usage 203260 # Number of bytes of host memory used
+host_seconds 1072.04 # Real time elapsed on the host
+host_tick_rate 2544665146 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.727991 # Number of seconds simulated