diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing')
4 files changed, 17 insertions, 44 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 896ad9c05..c29e7b8cc 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr index fd3c8e17c..b2d79346c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. +For more information see: http://www.m5sim.org/warn/d946bea6 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 15467090e..2a7a491ad 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,14 +5,15 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 4 2008 21:21:43 -M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652 -M5 commit date Thu Dec 04 18:04:32 2008 -0500 -M5 started Dec 4 2008 21:21:45 +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:36:09 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. spec_init Loading Input Data Input data 1048576 bytes in length diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 027e53548..b4009b3e6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1294592 # Simulator instruction rate (inst/s) -host_mem_usage 201124 # Number of bytes of host memory used -host_seconds 1405.68 # Real time elapsed on the host -host_tick_rate 1940692275 # Simulator tick rate (ticks/s) +host_inst_rate 2148631 # Simulator instruction rate (inst/s) +host_mem_usage 203048 # Number of bytes of host memory used +host_seconds 846.95 # Real time elapsed on the host +host_tick_rate 3220962828 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.015645 # ms system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000000 # ms system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # m system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 2751986 # number of replacements system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |