summaryrefslogtreecommitdiff
path: root/tests/long/60.bzip2/ref/alpha/tru64/simple-timing
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64/simple-timing')
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini13
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr6
-rwxr-xr-xtests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt26
4 files changed, 42 insertions, 13 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6c6b88ddd..6d6374beb 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -157,7 +166,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index 67f69f09d..79a2396a6 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -1,5 +1,11 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index d211942d5..b361f245f 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 21:30:55
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 21:53:28
-M5 executing on aus-bc2-b15
+M5 compiled Feb 7 2011 01:47:18
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:47:37
+M5 executing on burrito
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 7c181b6aa..f893b334a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2423488 # Simulator instruction rate (inst/s)
-host_mem_usage 239668 # Number of bytes of host memory used
-host_seconds 750.89 # Real time elapsed on the host
-host_tick_rate 3547033530 # Simulator tick rate (ticks/s)
+host_inst_rate 590383 # Simulator instruction rate (inst/s)
+host_mem_usage 225824 # Number of bytes of host memory used
+host_seconds 3082.37 # Real time elapsed on the host
+host_tick_rate 864089077 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.663444 # Number of seconds simulated
@@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 582065656000 # Cy
system.cpu.l2cache.writebacks 1170923 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
+system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
+system.cpu.num_fp_insts 805526 # number of float instructions
+system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
+system.cpu.num_func_calls 33534877 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 1819780127 # Number of instructions executed
-system.cpu.num_refs 611922547 # Number of memory references
+system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
+system.cpu.num_int_insts 1725565901 # number of integer instructions
+system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
+system.cpu.num_load_insts 449492741 # Number of load instructions
+system.cpu.num_mem_refs 611922547 # number of memory refs
+system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------