diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/alpha/tru64')
9 files changed, 51 insertions, 33 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index f540ab7a3..b5c8ed0d7 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 26e42fa14..9f955a134 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 22 2009 13:11:07 -M5 revision e406bb83c56f 6682 default qtip tip syscall-ioctl.patch -M5 started Oct 22 2009 13:42:59 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:37:14 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d858d0b22..411912baf 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254978 # Simulator instruction rate (inst/s) -host_mem_usage 190768 # Number of bytes of host memory used -host_seconds 6808.60 # Real time elapsed on the host -host_tick_rate 109025257 # Simulator tick rate (ticks/s) +host_inst_rate 176404 # Simulator instruction rate (inst/s) +host_mem_usage 192532 # Number of bytes of host memory used +host_seconds 9841.32 # Real time elapsed on the host +host_tick_rate 75427820 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -103,6 +103,10 @@ system.cpu.dcache.demand_mshr_misses 9523666 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.997499 # Average percentage of cache occupancy +system.cpu.dcache.occ_%::1 -0.003145 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4085.757368 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -12.883149 # Average occupied blocks per context system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency @@ -209,6 +213,8 @@ system.cpu.icache.demand_mshr_misses 902 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.347376 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 711.425375 # Average occupied blocks per context system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency @@ -399,6 +405,10 @@ system.cpu.l2cache.demand_mshr_misses 3773319 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.453663 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.336804 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 14865.634361 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11036.400552 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 4a349e817..8eb2ad76d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 3b9fb39a4..b436e5a76 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:59:02 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:01:37 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 81d14da53..279d75547 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3729984 # Simulator instruction rate (inst/s) -host_mem_usage 195632 # Number of bytes of host memory used -host_seconds 487.88 # Real time elapsed on the host -host_tick_rate 1871753572 # Simulator tick rate (ticks/s) +host_inst_rate 1736234 # Simulator instruction rate (inst/s) +host_mem_usage 184024 # Number of bytes of host memory used +host_seconds 1048.12 # Real time elapsed on the host +host_tick_rate 871264314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index fd5428b3a..dc20618d9 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 154e8b6b0..34965adea 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:13:47 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:20:02 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 106a8a8a6..a48cc62c7 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2540644 # Simulator instruction rate (inst/s) -host_mem_usage 204972 # Number of bytes of host memory used -host_seconds 716.27 # Real time elapsed on the host -host_tick_rate 3808619272 # Simulator tick rate (ticks/s) +host_inst_rate 1190978 # Simulator instruction rate (inst/s) +host_mem_usage 191664 # Number of bytes of host memory used +host_seconds 1527.97 # Real time elapsed on the host +host_tick_rate 1785366772 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9470216 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.996068 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4079.892573 # Average occupied blocks per context system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.298700 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 611.737435 # Average occupied blocks per context system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 3764493 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.438454 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.335641 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 14367.257286 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10998.286802 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |