diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/arm/linux')
12 files changed, 0 insertions, 1832 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini deleted file mode 100644 index 669a8b83b..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ /dev/null @@ -1,535 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -store_set_clear_period=250000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout deleted file mode 100755 index 1474108e5..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ /dev/null @@ -1,27 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:36:09 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 483463019500 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt deleted file mode 100644 index bd2b3efef..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ /dev/null @@ -1,536 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.483463 # Number of seconds simulated -sim_ticks 483463019500 # Number of ticks simulated -final_tick 483463019500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152421 # Simulator instruction rate (inst/s) -host_tick_rate 42766664 # Simulator tick rate (ticks/s) -host_mem_usage 220608 # Number of bytes of host memory used -host_seconds 11304.67 # Real time elapsed on the host -sim_insts 1723073849 # Number of instructions simulated -system.physmem.bytes_read 188174592 # Number of bytes read from this memory -system.physmem.bytes_inst_read 45888 # Number of instructions bytes read from this memory -system.physmem.bytes_written 77926272 # Number of bytes written to this memory -system.physmem.num_reads 2940228 # Number of read requests responded to by this memory -system.physmem.num_writes 1217598 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 389222307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 94915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 161183522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 550405829 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 966926040 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued -system.cpu.iq.rate 2.087542 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 18504 # number of nop insts executed -system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed -system.cpu.iew.exec_branches 238650211 # Number of branches executed -system.cpu.iew.exec_stores 191202715 # Number of stores executed -system.cpu.iew.exec_rate 2.054022 # Inst execution rate -system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1288034280 # num instructions producing a value -system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle -system.cpu.commit.count 1723073867 # Number of instructions committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773817 # Number of memory references committed -system.cpu.commit.loads 485926771 # Number of loads committed -system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462365 # Number of branches committed -system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. -system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2977240585 # The number of ROB reads -system.cpu.rob.rob_writes 4444170390 # The number of ROB writes -system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073849 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated -system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads -system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads -system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes -system.cpu.fp_regfile_reads 117 # number of floating regfile reads -system.cpu.fp_regfile_writes 59 # number of floating regfile writes -system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads -system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use -system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits -system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits -system.cpu.icache.overall_hits 285044064 # number of overall hits -system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses -system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9570827 # number of replacements -system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use -system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 666909088 # number of overall hits -system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15639225 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128328 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6064302 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2927819 # number of replacements -system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6635428 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940239 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217598 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index bbede2479..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,102 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=AtomicSimpleCPU -children=dtb itb tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -simulate_data_stalls=false -simulate_inst_stalls=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index e599bde0b..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,27 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:37:28 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 861538205000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index e23300649..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,87 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.861538 # Number of seconds simulated -sim_ticks 861538205000 # Number of ticks simulated -final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3027828 # Simulator instruction rate (inst/s) -host_tick_rate 1513916118 # Simulator tick rate (ticks/s) -host_mem_usage 210380 # Number of bytes of host memory used -host_seconds 569.08 # Real time elapsed on the host -sim_insts 1723073862 # Number of instructions simulated -system.physmem.bytes_read 7759650064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 624158392 # Number of bytes written to this memory -system.physmem.num_reads 2026949786 # Number of read requests responded to by this memory -system.physmem.num_writes 172586108 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9006739363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7171199555 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 724469778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9731209141 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1723076411 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1723073862 # Number of instructions executed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1723076411 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles - ----------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index 71abd898d..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,205 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=cpu membus physmem -mem_mode=atomic -memories=system.physmem -num_work_ids=16 -physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.port[0] - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload -checker=Null -clock=500 -cpu_id=0 -defer_registration=false -do_checkpoint_insts=true -do_statistics_insts=true -dtb=system.cpu.dtb -function_trace=false -function_trace_start=0 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -phase=0 -progress_interval=0 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=262144 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.dtb] -type=ArmTLB -size=64 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=131072 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.itb] -type=ArmTLB -size=64 - -[system.cpu.l2cache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=2 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=2097152 -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] - -[system.cpu.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side - -[system.cpu.tracer] -type=ExeTracer - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.membus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index e45cd058f..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout deleted file mode 100755 index 8198567b7..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,27 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 09:45:39 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2431419954000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 04e3122e6..000000000 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,280 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.431420 # Number of seconds simulated -sim_ticks 2431419954000 # Number of ticks simulated -final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1410228 # Simulator instruction rate (inst/s) -host_tick_rate 1996689457 # Simulator tick rate (ticks/s) -host_mem_usage 219344 # Number of bytes of host memory used -host_seconds 1217.73 # Real time elapsed on the host -sim_insts 1717270343 # Number of instructions simulated -system.physmem.bytes_read 172766016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75006720 # Number of bytes written to this memory -system.physmem.num_reads 2699469 # Number of read requests responded to by this memory -system.physmem.num_writes 1171980 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s) -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4862839908 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1717270343 # Number of instructions executed -system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330134 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498066 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941850 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773816 # number of memory refs -system.cpu.num_load_insts 485926770 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4862839908 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1544564961 # number of ReadReq hits -system.cpu.icache.demand_hits 1544564961 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1544564961 # number of overall hits -system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses -system.cpu.icache.demand_misses 638 # number of demand (read+write) misses -system.cpu.icache.overall_misses 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1544565599 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1544565599 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 475158040 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 645854938 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 645854938 # number of overall hits -system.cpu.dcache.ReadReq_misses 7226087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses 9115236 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177140908000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 240965130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 240965130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 482384127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 654970174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26435.424162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3061985 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 213619422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 213619422000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2687066 # number of replacements -system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15027.621217 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11106.896016 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.458607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.338956 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5417164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3061985 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 999241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6416405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6416405 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1809561 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889908 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2699469 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2699469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94097172000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46275216000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140372388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140372388000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7226725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3061985 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9115874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250398 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.471063 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.296128 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.296128 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171980 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1809561 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889908 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2699469 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2699469 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72382440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35596320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 107978760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 107978760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250398 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.296128 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.296128 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- |