diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/arm')
10 files changed, 120 insertions, 36 deletions
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 3ef4a25fb..731b0df43 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 2f2c51bdb..e9bf20924 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:57:47 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ab126a693..24c1e17c3 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165173 # Simulator instruction rate (inst/s) -host_mem_usage 251872 # Number of bytes of host memory used -host_seconds 10349.18 # Real time elapsed on the host -host_tick_rate 71148819 # Simulator tick rate (ticks/s) +host_inst_rate 152870 # Simulator instruction rate (inst/s) +host_mem_usage 238404 # Number of bytes of host memory used +host_seconds 11182.08 # Real time elapsed on the host +host_tick_rate 65849295 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.736332 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle system.cpu.commit.COM:count 1709408682 # Number of instructions committed +system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1523276792 # Number of committed integer instructions. system.cpu.commit.COM:loads 485926830 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 660773875 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 66 # number of floating regfile reads +system.cpu.fp_regfile_writes 62 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 145359637 # system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 5217275964 # number of integer regfile reads +system.cpu.int_regfile_writes 1582136898 # number of integer regfile writes system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 78 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 2136057911 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5702380947 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 2009251443 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3154359191 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 102861524 # Nu system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 3121183601 # number of misc regfile reads +system.cpu.misc_regfile_writes 895 # number of misc regfile writes system.cpu.numCycles 1472664444 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full @@ -477,10 +496,14 @@ system.cpu.rename.RENAME:RunCycles 526018927 # Nu system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1008 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 7136668460 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3717337450 # The number of ROB reads +system.cpu.rob.rob_writes 4979785274 # The number of ROB writes system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 14dc84cb3..8d90d74d0 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout index 9eea795e5..1ce869a83 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:23 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 11106ff07..8d3a8d25e 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2718053 # Simulator instruction rate (inst/s) -host_mem_usage 254288 # Number of bytes of host memory used -host_seconds 628.91 # Real time elapsed on the host -host_tick_rate 1359028059 # Simulator tick rate (ticks/s) +host_inst_rate 1030645 # Simulator instruction rate (inst/s) +host_mem_usage 229520 # Number of bytes of host memory used +host_seconds 1658.58 # Real time elapsed on the host +host_tick_rate 515323054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1709408682 # Number of instructions simulated sim_seconds 0.854706 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1709411231 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1709411231 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1709408682 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 4636623941 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065665 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini index d8eed8875..3f9e59a85 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr index eabe42249..cdafa164c 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout index fd7ecdb8c..ba8cd6dca 100755 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:48:19 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 4a18c77a9..923e9c734 100644 --- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 640383 # Simulator instruction rate (inst/s) -host_mem_usage 262008 # Number of bytes of host memory used -host_seconds 2660.29 # Real time elapsed on the host -host_tick_rate 913967481 # Simulator tick rate (ticks/s) +host_inst_rate 495941 # Simulator instruction rate (inst/s) +host_mem_usage 237232 # Number of bytes of host memory used +host_seconds 3435.10 # Real time elapsed on the host +host_tick_rate 707817123 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1703605163 # Number of instructions simulated sim_seconds 2.431420 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 538044067000 # Cy system.cpu.l2cache.writebacks 1171981 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4862840230 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4862840230 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1703605163 # Number of instructions executed -system.cpu.num_refs 660773876 # Number of memory references +system.cpu.num_int_alu_accesses 1523276793 # Number of integer alu accesses +system.cpu.num_int_insts 1523276793 # number of integer instructions +system.cpu.num_int_register_reads 5115465619 # number of times the integer registers were read +system.cpu.num_int_register_writes 1316065727 # number of times the integer registers were written +system.cpu.num_load_insts 485926830 # Number of load instructions +system.cpu.num_mem_refs 660773876 # number of memory refs +system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ---------- |