diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 103b5bcb4..129e4b866 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1577505 # Simulator instruction rate (inst/s) -host_mem_usage 207544 # Number of bytes of host memory used -host_seconds 2949.71 # Real time elapsed on the host -host_tick_rate 2030054219 # Simulator tick rate (ticks/s) +host_inst_rate 1178978 # Simulator instruction rate (inst/s) +host_mem_usage 205796 # Number of bytes of host memory used +host_seconds 3946.92 # Real time elapsed on the host +host_tick_rate 1517149915 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653176270 # Number of instructions simulated +sim_insts 4653327894 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated sim_ticks 5988064038000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 4737814312000 # C system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11976128076 # number of cpu cycles simulated -system.cpu.num_insts 4653176270 # Number of instructions executed +system.cpu.num_insts 4653327894 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls |