diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 5c98d4cbd..6bbf1280e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1139442 # Simulator instruction rate (inst/s) -host_mem_usage 201800 # Number of bytes of host memory used -host_seconds 4083.77 # Real time elapsed on the host -host_tick_rate 1872105757 # Simulator tick rate (ticks/s) +host_inst_rate 483951 # Simulator instruction rate (inst/s) +host_mem_usage 204540 # Number of bytes of host memory used +host_seconds 9614.98 # Real time elapsed on the host +host_tick_rate 795135330 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653219791 # Number of instructions simulated -sim_seconds 7.645253 # Number of seconds simulated -sim_ticks 7645253019000 # Number of ticks simulated +sim_insts 4653176258 # Number of instructions simulated +sim_seconds 7.645209 # Number of seconds simulated +sim_ticks 7645209486000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -76,14 +76,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.377593 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 78020119000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 5670378338 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5670377663 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -92,16 +92,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8400559.500741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5670378338 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5670377663 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -112,11 +112,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5670378338 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5670421196 # number of overall hits +system.cpu.icache.overall_hits 5670377663 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use -system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.334555 # Cycle average of tags in use +system.cpu.icache.total_refs 5670377663 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,13 +221,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25740.146811 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 6038871723000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15290506038 # number of cpu cycles simulated -system.cpu.num_insts 4653219791 # Number of instructions executed +system.cpu.numCycles 15290418972 # number of cpu cycles simulated +system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1686313781 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls |