diff options
Diffstat (limited to 'tests/long/60.bzip2/ref/x86')
6 files changed, 29 insertions, 18 deletions
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 8cd09b7fa..d7e2d0edd 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 583e2baa8..84cb84ccc 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:57:51 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 8024dc3cd..46cb78389 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1851230 # Simulator instruction rate (inst/s) -host_mem_usage 198160 # Number of bytes of host memory used -host_seconds 2513.64 # Real time elapsed on the host -host_tick_rate 1125554314 # Simulator tick rate (ticks/s) +host_inst_rate 1880958 # Simulator instruction rate (inst/s) +host_mem_usage 188832 # Number of bytes of host memory used +host_seconds 2473.91 # Real time elapsed on the host +host_tick_rate 1143628848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653327894 # Number of instructions simulated sim_seconds 2.829240 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index d5c949c6e..734089aa9 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -45,6 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -79,6 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -113,6 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -154,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 8e0139bb7..8794a16bf 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 8 2009 16:16:58 -M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff -M5 started Nov 8 2009 16:30:56 -M5 executing on maize +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:58:19 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index ffd34c1e6..d56c14beb 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1485872 # Simulator instruction rate (inst/s) -host_mem_usage 194272 # Number of bytes of host memory used -host_seconds 3131.72 # Real time elapsed on the host -host_tick_rate 1912063349 # Simulator tick rate (ticks/s) +host_inst_rate 1049992 # Simulator instruction rate (inst/s) +host_mem_usage 196480 # Number of bytes of host memory used +host_seconds 4431.78 # Real time elapsed on the host +host_tick_rate 1351159917 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653327894 # Number of instructions simulated sim_seconds 5.988038 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 9469303 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.997259 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4084.774232 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32370.287021 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 555.573148 # Average occupied blocks per context system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 3785130 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.437806 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.347809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 14346.014207 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11397.001683 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 9112667 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |