diff options
Diffstat (limited to 'tests/long/60.bzip2/ref')
-rwxr-xr-x | tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 6 | ||||
-rw-r--r-- | tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 148 |
2 files changed, 77 insertions, 77 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index d46e4c412..84bba46f1 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:10:17 +M5 compiled Jul 6 2009 11:03:45 +M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip +M5 started Jul 6 2009 11:56:32 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 8a66d53b4..3a8e7864a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 225916 # Simulator instruction rate (inst/s) -host_mem_usage 205860 # Number of bytes of host memory used -host_seconds 7684.48 # Real time elapsed on the host -host_tick_rate 96598522 # Simulator tick rate (ticks/s) +host_inst_rate 222565 # Simulator instruction rate (inst/s) +host_mem_usage 190364 # Number of bytes of host memory used +host_seconds 7800.15 # Real time elapsed on the host +host_tick_rate 95165996 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -20,22 +20,22 @@ system.cpu.commit.COM:branches 214632552 # Nu system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle::samples 1379215339 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 736540831 53.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 260049504 18.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 126970462 9.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 77723426 5.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 51327439 3.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 27759546 2.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 26179568 1.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 9881978 0.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 62782585 4.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1379215339 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 1.319431 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 2.090314 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 736540831 53.40% 53.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 260049504 18.85% 72.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 126970462 9.21% 81.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 77723426 5.64% 87.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 51327439 3.72% 90.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 27759546 2.01% 92.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 26179568 1.90% 94.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 9881978 0.72% 95.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 62782585 4.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1379215339 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed system.cpu.commit.COM:loads 445666361 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -160,22 +160,22 @@ system.cpu.fetch.icacheStallCycles 355180518 # Nu system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 1472299541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 907273323 61.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 47886355 3.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 34613456 2.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 52095475 3.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 125971058 8.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 69335096 4.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 50458684 3.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 40993758 2.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 143672336 9.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1472299541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.944609 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.837831 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 907273323 61.62% 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 47886355 3.25% 64.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 34613456 2.35% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 52095475 3.54% 70.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 125971058 8.56% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 69335096 4.71% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 50458684 3.43% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 40993758 2.78% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 143672336 9.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1472299541 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency @@ -275,54 +275,54 @@ system.cpu.iew.predictedNotTakenIncorrect 703796 # N system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920254 66.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 99 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 143 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 577889733 24.95% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 205034377 8.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920254 66.19% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 99 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 143 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 577889733 24.95% 91.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 205034377 8.85% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::total 2315844900 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2738956 19.03% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 9224843 64.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2429770 16.88% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2738956 19.03% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 9224843 64.09% 83.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 2429770 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% 39.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% 57.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% 74.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% 83.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% 91.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% 96.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% 99.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued |