diff options
Diffstat (limited to 'tests/long/60.bzip2/ref')
5 files changed, 124 insertions, 127 deletions
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 84bba46f1..26e42fa14 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:56:32 +M5 compiled Oct 22 2009 13:11:07 +M5 revision e406bb83c56f 6682 default qtip tip syscall-ioctl.patch +M5 started Oct 22 2009 13:42:59 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 3a8e7864a..d858d0b22 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 222565 # Simulator instruction rate (inst/s) -host_mem_usage 190364 # Number of bytes of host memory used -host_seconds 7800.15 # Real time elapsed on the host -host_tick_rate 95165996 # Simulator tick rate (ticks/s) +host_inst_rate 254978 # Simulator instruction rate (inst/s) +host_mem_usage 190768 # Number of bytes of host memory used +host_seconds 6808.60 # Real time elapsed on the host +host_tick_rate 109025257 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -133,17 +133,17 @@ system.cpu.decode.DECODE:RunCycles 549143104 # Nu system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 768331639 # DTB accesses +system.cpu.dtb.data_accesses 768331641 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 752318838 # DTB hits +system.cpu.dtb.data_hits 752318840 # DTB hits system.cpu.dtb.data_misses 16012801 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 566617551 # DTB read accesses +system.cpu.dtb.read_accesses 566617553 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 557381525 # DTB read hits +system.cpu.dtb.read_hits 557381527 # DTB read hits system.cpu.dtb.read_misses 9236026 # DTB read misses system.cpu.dtb.write_accesses 201714088 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations @@ -234,17 +234,17 @@ system.cpu.idleCycles 12319311 # To system.cpu.iew.EXEC:branches 282186314 # Number of branches executed system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate -system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed +system.cpu.iew.EXEC:refs 769619326 # number of memory reference insts executed system.cpu.iew.EXEC:stores 201925301 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value -system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1531990764 # num instructions consuming a value +system.cpu.iew.WB:count 2240290245 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1243717865 # num instructions producing a value +system.cpu.iew.WB:producers 1243717866 # num instructions producing a value system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle -system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent 2261678943 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions @@ -252,9 +252,9 @@ system.cpu.iew.iewDispNonSpecInsts 43 # Nu system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 567694025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 36858071 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2278986831 # Number of executed instructions system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall @@ -262,7 +262,7 @@ system.cpu.iew.iewSquashCycles 93084202 # Nu system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 33889598 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address @@ -276,7 +276,7 @@ system.cpu.iew.predictedTakenIncorrect 20638338 # Nu system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920254 66.19% 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920256 66.19% 66.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 99 0.00% 66.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 66.19% # Type of FU issued @@ -289,7 +289,7 @@ system.cpu.iq.ISSUE:FU_type_0::MemRead 577889733 24.95% 91.15% # Ty system.cpu.iq.ISSUE:FU_type_0::MemWrite 205034377 8.85% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2315844900 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 2315844902 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available @@ -311,9 +311,9 @@ system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 # system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% 39.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% 57.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543755 18.44% 57.68% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% 74.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% 83.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713875 9.49% 83.67% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% 91.95% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% 96.69% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% 99.38% # Number of insts issued each cycle @@ -325,12 +325,12 @@ system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2315844902 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 329349452 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index 2985d5b21..d5c949c6e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index ea6185a03..8e0139bb7 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:13:11 -M5 executing on tater +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:30:56 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5988064038000 because target called exit() +Exiting @ tick 5988037845000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 129e4b866..ffd34c1e6 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1178978 # Simulator instruction rate (inst/s) -host_mem_usage 205796 # Number of bytes of host memory used -host_seconds 3946.92 # Real time elapsed on the host -host_tick_rate 1517149915 # Simulator tick rate (ticks/s) +host_inst_rate 1485872 # Simulator instruction rate (inst/s) +host_mem_usage 194272 # Number of bytes of host memory used +host_seconds 3131.72 # Real time elapsed on the host +host_tick_rate 1912063349 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653327894 # Number of instructions simulated -sim_seconds 5.988064 # Number of seconds simulated -sim_ticks 5988064038000 # Number of ticks simulated +sim_seconds 5.988038 # Number of seconds simulated +sim_ticks 5988037845000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 25018.463901 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22018.463901 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231962487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180689726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005828 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222255 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159022961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005828 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222255 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55999.840680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.840680 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436281288 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125834330000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 2247048 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119093186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2247048 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 183.121439 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 32370.287021 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668243775 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306524056000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005644 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9469303 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 278116147000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005644 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9469303 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 32370.287021 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668242528 # number of overall hits -system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470550 # number of overall misses +system.cpu.dcache.overall_hits 1668243775 # number of overall hits +system.cpu.dcache.overall_miss_latency 306524056000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005644 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9469303 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 278116147000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005644 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9469303 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9108982 # number of replacements -system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9107896 # number of replacements +system.cpu.dcache.sampled_refs 9111992 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.778553 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58863931000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244013 # number of writebacks +system.cpu.dcache.tagsinuse 4084.774232 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668601086 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58863918000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2243955 # number of writebacks system.cpu.icache.ReadReq_accesses 4013232890 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.573148 # Cycle average of tags in use system.cpu.icache.total_refs 4013232215 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1889737 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 98266324000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1889737 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75589480000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 1889737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7222930 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 5327537 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98560436000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262413 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895393 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75815720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262413 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895393 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357311 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.899729 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 18561556000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 357311 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14292440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 357311 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2243955 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2243955 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.380966 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 9112667 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5327537 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196826760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785130 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 151405200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785130 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 9112667 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5328546 # number of overall hits -system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3785207 # number of overall misses +system.cpu.l2cache.overall_hits 5327537 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196826760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785130 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 151405200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785130 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2772128 # number of replacements -system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2771977 # number of replacements +system.cpu.l2cache.sampled_refs 2798150 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25742.940388 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4737814312000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1199171 # number of writebacks +system.cpu.l2cache.tagsinuse 25743.015890 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6662299 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4737770578000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199166 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11976128076 # number of cpu cycles simulated +system.cpu.numCycles 11976075690 # number of cpu cycles simulated system.cpu.num_insts 4653327894 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls |