diff options
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 64 |
1 files changed, 33 insertions, 31 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 485a8a7d7..21c5777d8 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13008791 # Number of BTB hits -global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -global.BPredUnit.lookups 19468548 # Number of BP lookups -global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. -host_inst_rate 179748 # Simulator instruction rate (inst/s) -host_mem_usage 209188 # Number of bytes of host memory used -host_seconds 468.32 # Real time elapsed on the host -host_tick_rate 87159490 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. +host_inst_rate 205423 # Simulator instruction rate (inst/s) +host_mem_usage 211084 # Number of bytes of host memory used +host_seconds 409.79 # Real time elapsed on the host +host_tick_rate 99609545 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040819 # Number of seconds simulated sim_ticks 40818658500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35305774 4330.49% - 1 18904885 2318.81% - 2 11574997 1419.75% - 3 6762756 829.50% - 4 5075415 622.53% - 5 2394533 293.71% - 6 1208963 148.29% - 7 250769 30.76% - 8 50251 6.16% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% +system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued @@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 2244.769579 # Cy system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 81637318 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed |