diff options
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index c77e086b4..e5dfef14d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2902114 # Simulator instruction rate (inst/s) -host_mem_usage 207972 # Number of bytes of host memory used -host_seconds 31.67 # Real time elapsed on the host -host_tick_rate 3749775750 # Simulator tick rate (ticks/s) +host_inst_rate 2783619 # Simulator instruction rate (inst/s) +host_mem_usage 209832 # Number of bytes of host memory used +host_seconds 33.02 # Real time elapsed on the host +host_tick_rate 3596666384 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated @@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 1442.022508 # Cy system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks -system.cpu.dtb.accesses 26497334 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 26497301 # DTB hits -system.cpu.dtb.misses 33 # DTB misses +system.cpu.dtb.data_accesses 26497334 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 26497301 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 19996208 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 19996198 # DTB read hits @@ -137,10 +141,22 @@ system.cpu.icache.total_refs 91894580 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 91903137 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 91903090 # ITB hits -system.cpu.itb.misses 47 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 91903137 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 91903090 # ITB hits +system.cpu.itb.fetch_misses 47 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency |