diff options
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 2aaa18b18..ea7e649f7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 559604 # Simulator instruction rate (inst/s) -host_mem_usage 229724 # Number of bytes of host memory used -host_seconds 164.23 # Real time elapsed on the host -host_tick_rate 723015392 # Simulator tick rate (ticks/s) +host_inst_rate 2623121 # Simulator instruction rate (inst/s) +host_mem_usage 207408 # Number of bytes of host memory used +host_seconds 35.04 # Real time elapsed on the host +host_tick_rate 3389091421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2223 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 4765 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 62575473 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_mem_refs 26497334 # number of memory refs system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 389 # Number of system calls +system.cpu.workload.num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- |