diff options
Diffstat (limited to 'tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 142 |
1 files changed, 67 insertions, 75 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b08531811..fb91662b2 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1269659 # Simulator instruction rate (inst/s) -host_mem_usage 210612 # Number of bytes of host memory used -host_seconds 72.38 # Real time elapsed on the host -host_tick_rate 1640438984 # Simulator tick rate (ticks/s) +host_inst_rate 1097596 # Simulator instruction rate (inst/s) +host_mem_usage 196804 # Number of bytes of host memory used +host_seconds 83.73 # Real time elapsed on the host +host_tick_rate 1418103765 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118742 # Number of seconds simulated -sim_ticks 118742021000 # Number of ticks simulated +sim_seconds 0.118740 # Number of seconds simulated +sim_ticks 118740049000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 98784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 93492000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55005.806163 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123158000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 116441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352059 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1442.035674 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55005.806163 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495062 # number of overall hits -system.cpu.dcache.overall_miss_latency 123158000 # number of overall miss cycles +system.cpu.dcache.overall_hits 26495078 # number of overall hits +system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2239 # number of overall misses +system.cpu.dcache.overall_misses 2223 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 116441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1442.035674 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.dcache.writebacks 107 # number of writebacks system.cpu.dtb.data_accesses 26497334 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 26497301 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.692403 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1418.041181 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.041181 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,12 +164,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -180,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses 3043 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 832000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 640000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.909179 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2056.260143 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.724287 # Average occupied blocks per context +system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5942 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4791 # number of overall misses +system.cpu.l2cache.overall_hits 5968 # number of overall hits +system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4765 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3105 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2069.984431 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237484042 # number of cpu cycles simulated +system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls |