summaryrefslogtreecommitdiff
path: root/tests/long/70.twolf/ref/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/70.twolf/ref/alpha')
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt16
2 files changed, 11 insertions, 11 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index d9d5fef40..0f49fe322 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 27 2010 01:41:24
-M5 revision e00bda288de7 7046 default qtip tip update_regrs
-M5 started Mar 27 2010 01:46:24
+M5 compiled Apr 10 2010 23:44:54
+M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip
+M5 started Apr 10 2010 23:44:56
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 7f83ef7d8..3d8fcc484 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 50762 # Simulator instruction rate (inst/s)
-host_mem_usage 156288 # Number of bytes of host memory used
-host_seconds 1810.49 # Real time elapsed on the host
-host_tick_rate 54563823 # Simulator tick rate (ticks/s)
+host_inst_rate 45830 # Simulator instruction rate (inst/s)
+host_mem_usage 156280 # Number of bytes of host memory used
+host_seconds 2005.28 # Real time elapsed on the host
+host_tick_rate 49263361 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.098787 # Number of seconds simulated
@@ -30,7 +30,7 @@ system.cpu.Graduation-Unit.instReqsProcessed 91903056
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 196150555 # Number of Instructions Requests that completed in this resource.
+system.cpu.RegFile-Manager.instReqsProcessed 196150553 # Number of Instructions Requests that completed in this resource.
system.cpu.activity 96.136450 # Percentage of cycles cpu is active
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
@@ -284,9 +284,9 @@ system.cpu.stage-0.utilization 52.274318 # Pe
system.cpu.stage-1.idleCycles 105572319 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 92001832 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 46.565723 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 104081665 # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles 93492486 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 47.320201 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 104081667 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-2.utilization 47.320200 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 171037020 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 13.431479 # Percentage of cycles stage was utilized (processing insts).