diff options
Diffstat (limited to 'tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt | 126 |
1 files changed, 59 insertions, 67 deletions
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index 156b8dc2a..ea6f10d3a 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1713926 # Simulator instruction rate (inst/s) -host_mem_usage 214560 # Number of bytes of host memory used -host_seconds 108.72 # Real time elapsed on the host -host_tick_rate 2134224518 # Simulator tick rate (ticks/s) +host_inst_rate 1260082 # Simulator instruction rate (inst/s) +host_mem_usage 200384 # Number of bytes of host memory used +host_seconds 147.87 # Real time elapsed on the host +host_tick_rate 1569082964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186333855 # Number of instructions simulated sim_seconds 0.232028 # Number of seconds simulated -sim_ticks 232028062000 # Number of ticks simulated +sim_ticks 232027671000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 34134000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 690 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 12385593 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 12385594 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54639.865997 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency -system.cpu.dcache.demand_hits 42025083 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97860000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54451.396648 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency +system.cpu.dcache.demand_hits 42025084 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97468000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1791 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1790 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 92487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 92098000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1791 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1790 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.333155 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1364.601520 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 1364.601667 # Average occupied blocks per context system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54639.865997 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54451.396648 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 42025083 # number of overall hits -system.cpu.dcache.overall_miss_latency 97860000 # number of overall miss cycles +system.cpu.dcache.overall_hits 42025084 # number of overall hits +system.cpu.dcache.overall_miss_latency 97468000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1791 # number of overall misses +system.cpu.dcache.overall_misses 1790 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 92487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 92098000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1791 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1790 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 40 # number of replacements system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1364.601520 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1364.601667 # Cycle average of tags in use system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 16 # number of writebacks @@ -115,7 +115,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.560536 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1147.977742 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1147.977892 # Average occupied blocks per context system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1506 # number of replacements system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1147.977742 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.977892 # Cycle average of tags in use system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 57200000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1100 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 44000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1100 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 3741 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -166,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses 2361 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 52000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 40000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.582348 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 4841 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1380 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.714935 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3461 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1388 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.713282 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 138440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.714935 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3461 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.713282 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1672.604273 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2.043764 # Average occupied blocks per context +system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1672.604511 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.037968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1380 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179972000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.714935 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3461 # number of overall misses +system.cpu.l2cache.overall_hits 1388 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.713282 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3453 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 138440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.714935 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3461 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.713282 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2368 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 1674.648036 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1675.642479 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 464056124 # number of cpu cycles simulated +system.cpu.numCycles 464055342 # number of cpu cycles simulated system.cpu.num_insts 186333855 # Number of instructions executed system.cpu.num_refs 42511846 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |