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-rw-r--r--tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini13
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt31
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini15
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-atomic/simout14
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt26
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini15
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-timing/simerr10
-rwxr-xr-xtests/long/70.twolf/ref/arm/linux/simple-timing/simout14
-rw-r--r--tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt26
10 files changed, 132 insertions, 40 deletions
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index 95580ac45..f95eb4d89 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=DerivO3CPU
@@ -484,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index 832370508..46dd2c791 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 04:18:31
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 02:00:24
+M5 executing on burrito
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index a8b50fb87..21ada4fbc 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 96216 # Simulator instruction rate (inst/s)
-host_mem_usage 255460 # Number of bytes of host memory used
-host_seconds 1920.75 # Real time elapsed on the host
-host_tick_rate 78000522 # Simulator tick rate (ticks/s)
+host_inst_rate 61621 # Simulator instruction rate (inst/s)
+host_mem_usage 241964 # Number of bytes of host memory used
+host_seconds 2999.07 # Real time elapsed on the host
+host_tick_rate 49955205 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 184806751 # Number of instructions simulated
sim_seconds 0.149819 # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 285162307 # Number of insts commited each cycle
system.cpu.commit.COM:count 184806751 # Number of instructions committed
+system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
+system.cpu.commit.COM:int_insts 146860811 # Number of committed integer instructions.
system.cpu.commit.COM:loads 29554611 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 42081439 # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 299566319 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 2799107 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2446180 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25129.997165 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430 # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 2461724 #
system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1407561 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 457836856 # number of integer regfile reads
+system.cpu.int_regfile_writes 195349958 # number of integer regfile writes
system.cpu.ipc 0.616766 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.616766 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 299566319 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.711320 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 1965612 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 3923910 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1824312 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 2255873 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 212345848 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 723342864 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 197666637 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 240391153 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 220060942 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 213138842 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 3889323 # Nu
system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 14988552 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 328971278 # number of misc regfile reads
+system.cpu.misc_regfile_writes 4891827 # number of misc regfile writes
system.cpu.numCycles 299638437 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full
@@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 190277990 # Nu
system.cpu.rename.RENAME:SquashCycles 14404012 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1750038 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 71145762 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 14827185 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 586253105 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 506291228 # The number of ROB reads
+system.cpu.rob.rob_writes 457856948 # The number of ROB writes
system.cpu.timesIdled 1363 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 9f4b7679d..283406dc2 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@@ -52,12 +61,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index 4f3382663..c50fadfb0 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:22:41
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:56:35
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 45e4b8820..4a204d0cd 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2742393 # Simulator instruction rate (inst/s)
-host_mem_usage 257424 # Number of bytes of host memory used
-host_seconds 68.12 # Real time elapsed on the host
-host_tick_rate 1499949275 # Simulator tick rate (ticks/s)
+host_inst_rate 1012006 # Simulator instruction rate (inst/s)
+host_mem_usage 232796 # Number of bytes of host memory used
+host_seconds 184.60 # Real time elapsed on the host
+host_tick_rate 553516772 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186818826 # Number of instructions simulated
sim_seconds 0.102181 # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 204361469 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 204361469 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
+system.cpu.num_fp_insts 1752310 # number of float instructions
+system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 186818826 # Number of instructions executed
-system.cpu.num_refs 42511846 # Number of memory references
+system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses
+system.cpu.num_int_insts 148453796 # number of integer instructions
+system.cpu.num_int_register_reads 440904784 # number of times the integer registers were read
+system.cpu.num_int_register_writes 179338779 # number of times the integer registers were written
+system.cpu.num_load_insts 29867211 # Number of load instructions
+system.cpu.num_mem_refs 42511846 # number of memory refs
+system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index c7e80818a..d150b1761 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -152,12 +161,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
index eabe42249..83ecbdfc0 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,13 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index 60b3eda0f..5cb7e11c7 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 19:00:18
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:56:24
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index b971df920..715b30669 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 709254 # Simulator instruction rate (inst/s)
-host_mem_usage 265144 # Number of bytes of host memory used
-host_seconds 262.72 # Real time elapsed on the host
-host_tick_rate 883179772 # Simulator tick rate (ticks/s)
+host_inst_rate 504285 # Simulator instruction rate (inst/s)
+host_mem_usage 240500 # Number of bytes of host memory used
+host_seconds 369.50 # Real time elapsed on the host
+host_tick_rate 627947562 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186333855 # Number of instructions simulated
sim_seconds 0.232028 # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 464055342 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 464055342 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
+system.cpu.num_fp_insts 1752310 # number of float instructions
+system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 186333855 # Number of instructions executed
-system.cpu.num_refs 42511846 # Number of memory references
+system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses
+system.cpu.num_int_insts 148453796 # number of integer instructions
+system.cpu.num_int_register_reads 470866018 # number of times the integer registers were read
+system.cpu.num_int_register_writes 179570637 # number of times the integer registers were written
+system.cpu.num_load_insts 29867211 # Number of load instructions
+system.cpu.num_mem_refs 42511846 # number of memory refs
+system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------