diff options
Diffstat (limited to 'tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index ce58f98ef..791de009c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1857648 # Simulator instruction rate (inst/s) -host_mem_usage 211672 # Number of bytes of host memory used -host_seconds 104.13 # Real time elapsed on the host -host_tick_rate 2598354088 # Simulator tick rate (ticks/s) +host_inst_rate 890462 # Simulator instruction rate (inst/s) +host_mem_usage 197912 # Number of bytes of host memory used +host_seconds 217.24 # Real time elapsed on the host +host_tick_rate 1245520491 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270578 # Number of seconds simulated @@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses 1599 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.302049 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1237.193190 # Average occupied blocks per context system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.777132 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1591.566647 # Average occupied blocks per context system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency @@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses 5173 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.081095 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2657.327524 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.000455 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |