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-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini2
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out2
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt108
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr1
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout6
5 files changed, 59 insertions, 60 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 0e057cbbe..ec76ab996 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -12,7 +12,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
-clock=1
+clock=500
cpu_id=0
defer_registration=false
function_trace=false
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
index 5f60c76d0..dbecb5fa5 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
@@ -47,7 +47,7 @@ progress_interval=0
system=system
cpu_id=0
workload=system.cpu.workload
-clock=1
+clock=500
phase=0
defer_registration=false
// width not specified
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
index 2fbdef851..2c6679b72 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 471554 # Simulator instruction rate (inst/s)
-host_mem_usage 155352 # Number of bytes of host memory used
-host_seconds 410.21 # Real time elapsed on the host
-host_tick_rate 766692 # Simulator tick rate (ticks/s)
+host_inst_rate 490451 # Simulator instruction rate (inst/s)
+host_mem_usage 156012 # Number of bytes of host memory used
+host_seconds 394.40 # Real time elapsed on the host
+host_tick_rate 342594746 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated
-sim_seconds 0.000315 # Number of seconds simulated
-sim_ticks 314505003 # Number of ticks simulated
+sim_seconds 0.135121 # Number of seconds simulated
+sim_ticks 135120940500 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 76708968 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1584 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 26 # number of replacements
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 23 # number of writebacks
system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 193423706 # number of overall hits
-system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.overall_misses 12268 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 10342 # number of replacements
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use
system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
@@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 8708 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5167 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 314505003 # number of cpu cycles simulated
+system.cpu.numCycles 135120940500 # number of cpu cycles simulated
system.cpu.num_insts 193435973 # Number of instructions executed
system.cpu.num_refs 76732959 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
index 6e24f6d54..18e13818c 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
@@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x11e394 length 0x10.
warn: More than two loadable segments in ELF object.
warn: Ignoring segment @ 0x0 length 0x0.
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: Ignoring request to flush register windows.
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index d50dfc3c4..eb4e3bbfa 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -18,11 +18,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 29 2007 16:12:35
-M5 started Thu Mar 29 16:13:01 2007
+M5 compiled Apr 27 2007 14:35:32
+M5 started Fri Apr 27 16:08:41 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 314505003 because target called exit()
+Exiting @ tick 135120940500 because target called exit()