diff options
Diffstat (limited to 'tests/long/70.twolf/ref/sparc')
3 files changed, 132 insertions, 113 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 2a87cb78d..1e251ac7c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload +children=dcache icache l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false @@ -24,27 +24,28 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -52,12 +53,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -90,12 +89,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -128,12 +125,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -151,6 +146,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=twolf smred @@ -174,7 +172,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 0f4d2b473..7c9f3f182 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 500598 # Simulator instruction rate (inst/s) -host_mem_usage 156000 # Number of bytes of host memory used -host_seconds 386.41 # Real time elapsed on the host -host_tick_rate 699597163 # Simulator tick rate (ticks/s) +host_inst_rate 1154889 # Simulator instruction rate (inst/s) +host_mem_usage 206344 # Number of bytes of host memory used +host_seconds 167.49 # Real time elapsed on the host +host_tick_rate 1614378740 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.270332 # Number of seconds simulated -sim_ticks 270331639000 # Number of ticks simulated +sim_seconds 0.270398 # Number of seconds simulated +sim_ticks 270397855000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 12450000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 11454000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 27750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 25530000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks. @@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency -system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 40200000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 36984000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles +system.cpu.dcache.overall_hits 76708944 # number of overall hits +system.cpu.dcache.overall_miss_latency 40200000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1584 # number of overall misses +system.cpu.dcache.overall_misses 1608 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 36984000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.402461 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 178016000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 178016000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 178016000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,57 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.726914 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 23914000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 89914000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 550000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 23 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 23 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.136632 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 113828000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 56914000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.373493 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5167 # number of overall misses +system.cpu.l2cache.overall_hits 8679 # number of overall hits +system.cpu.l2cache.overall_miss_latency 113828000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 56914000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.373493 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -211,14 +232,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2649.703709 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270331639000 # number of cpu cycles simulated +system.cpu.numCycles 270397855000 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index 316a2c0d3..c89e9c783 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 16:53:38 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 12 2007 12:23:15 +M5 started Sun Aug 12 16:55:52 2007 +M5 executing on zeep command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 270331639000 because target called exit() +Exiting @ tick 270397855000 because target called exit() |