diff options
Diffstat (limited to 'tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 84b97ca66..e5f49060a 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 200454 # Simulator instruction rate (inst/s) -host_mem_usage 220376 # Number of bytes of host memory used -host_seconds 1104.31 # Real time elapsed on the host -host_tick_rate 96698720 # Simulator tick rate (ticks/s) +host_inst_rate 120975 # Simulator instruction rate (inst/s) +host_mem_usage 223752 # Number of bytes of host memory used +host_seconds 1829.83 # Real time elapsed on the host +host_tick_rate 58358040 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.106785 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 16343714 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 35659 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 45746 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 48346210 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 16601009 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 16343714 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 35659 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 45746 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 48346210 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 16601009 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly |