diff options
Diffstat (limited to 'tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 95 |
1 files changed, 48 insertions, 47 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 24bf72eb4..69e591ac8 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 935562 # Simulator instruction rate (inst/s) -host_mem_usage 217504 # Number of bytes of host memory used -host_seconds 234.54 # Real time elapsed on the host -host_tick_rate 1069990696 # Simulator tick rate (ticks/s) +host_inst_rate 1231791 # Simulator instruction rate (inst/s) +host_mem_usage 202836 # Number of bytes of host memory used +host_seconds 178.14 # Real time elapsed on the host +host_tick_rate 1408783027 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 219431024 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated -sim_ticks 250960757000 # Number of ticks simulated +sim_ticks 250960631000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency @@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 88368000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 83634000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55846.719160 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 106388000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 100672500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1363.451646 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55846.719160 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.overall_miss_latency 106388000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 1905 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100672500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -69,7 +69,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1363.451646 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 7 # number of writebacks @@ -106,7 +106,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1455.289171 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2836 # number of replacements system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.289171 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -132,12 +132,13 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 82056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1578 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -159,46 +160,46 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52003.271423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1861 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246391500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.717988 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4738 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 189520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.717988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4738 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2058.146657 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021757 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1861 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246391500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.717988 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4738 # number of overall misses +system.cpu.l2cache.overall_hits 1864 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4735 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.717988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4738 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2058.168414 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501921514 # number of cpu cycles simulated +system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.num_insts 219431024 # Number of instructions executed system.cpu.num_refs 77165306 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |