diff options
Diffstat (limited to 'tests/long/70.twolf/ref/x86')
8 files changed, 43 insertions, 65 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index b8de37bf3..d0a878165 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -49,7 +52,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr index 27f336eb4..94d399eab 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index eea857771..fd5d4825d 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,14 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:57:21 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:24:38 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,6 +17,8 @@ TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 90a051575..5f9bdeb8f 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 697777 # Simulator instruction rate (inst/s) -host_mem_usage 204448 # Number of bytes of host memory used -host_seconds 313.27 # Real time elapsed on the host -host_tick_rate 415001936 # Simulator tick rate (ticks/s) +host_inst_rate 1349784 # Simulator instruction rate (inst/s) +host_mem_usage 204760 # Number of bytes of host memory used +host_seconds 161.95 # Real time elapsed on the host +host_tick_rate 802781753 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 86cbaffb4..c231a2f5e 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -155,7 +155,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr index 27f336eb4..94d399eab 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -warn: Increasing stack size by one page. -warn: Increasing stack size by one page. -warn: be nice to actually delete the event here +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 6c4741848..c8bd5d18c 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,14 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 26 2008 18:29:56 -M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9 -M5 commit date Fri Dec 26 18:25:21 2008 -0800 -M5 started Dec 26 2008 19:12:20 -M5 executing on fajita -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +M5 compiled Feb 16 2009 00:19:15 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 01:27:21 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,6 +19,8 @@ TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University +info: Increasing stack size by one page. +info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 91975530b..21956901a 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 495446 # Simulator instruction rate (inst/s) -host_mem_usage 211916 # Number of bytes of host memory used -host_seconds 441.21 # Real time elapsed on the host -host_tick_rate 764874761 # Simulator tick rate (ticks/s) +host_inst_rate 1082313 # Simulator instruction rate (inst/s) +host_mem_usage 212196 # Number of bytes of host memory used +host_seconds 201.97 # Real time elapsed on the host +host_tick_rate 1670883730 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated sim_seconds 0.337470 # Number of seconds simulated @@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000018 # ms system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # m system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |