diff options
Diffstat (limited to 'tests/long/70.twolf/ref')
39 files changed, 471 insertions, 146 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 389a82884..8ab14c5fa 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=InOrderCPU diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 6bea6bb9d..2bd9f8140 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 24 2011 21:05:28 -M5 revision Unknown -M5 started Jan 24 2011 21:05:32 -M5 executing on m55-002.pool +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 81e378671..bb16b8b96 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66004 # Simulator instruction rate (inst/s) -host_mem_usage 1421192 # Number of bytes of host memory used -host_seconds 1392.38 # Real time elapsed on the host -host_tick_rate 29109416 # Simulator tick rate (ticks/s) +host_inst_rate 25888 # Simulator instruction rate (inst/s) +host_mem_usage 1480704 # Number of bytes of host memory used +host_seconds 3550.03 # Real time elapsed on the host +host_tick_rate 11417230 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated @@ -272,6 +272,8 @@ system.cpu.l2cache.total_refs 7072 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 81062947 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 74310489 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 02074cf40..01f3bf111 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 6d564a58f..b9f2d3d21 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:30:09 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 6e4f9aea5..2fcd0832c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 134338 # Simulator instruction rate (inst/s) -host_mem_usage 210480 # Number of bytes of host memory used -host_seconds 626.63 # Real time elapsed on the host -host_tick_rate 64841631 # Simulator tick rate (ticks/s) +host_inst_rate 68515 # Simulator instruction rate (inst/s) +host_mem_usage 230924 # Number of bytes of host memory used +host_seconds 1228.63 # Real time elapsed on the host +host_tick_rate 33070698 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040632 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed +system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed. +system.cpu.commit.COM:int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.COM:loads 19996198 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26497301 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 6156758 # number of floating regfile reads +system.cpu.fp_regfile_writes 6040765 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 4154704 # system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 137465323 # number of integer regfile reads +system.cpu.int_regfile_writes 75768353 # number of integer regfile writes system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate +system.cpu.iq.fp_alu_accesses 8012478 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 15186691 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 7058808 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 12278263 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 97954442 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 276254930 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 92993062 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 174004519 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17824866 # Nu system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 712336 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 81263024 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full @@ -470,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles 28432140 # Nu system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 11932541 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 190714138 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 218412469 # The number of ROB reads +system.cpu.rob.rob_writes 304705559 # The number of ROB writes system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index a6e47a29e..1801d3968 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index dc1519d82..06628f244 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:32:41 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 50ef29969..3667c8fef 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4196549 # Simulator instruction rate (inst/s) -host_mem_usage 235848 # Number of bytes of host memory used -host_seconds 21.90 # Real time elapsed on the host -host_tick_rate 2098254960 # Simulator tick rate (ticks/s) +host_inst_rate 1609489 # Simulator instruction rate (inst/s) +host_mem_usage 222008 # Number of bytes of host memory used +host_seconds 57.10 # Real time elapsed on the host +host_tick_rate 804741446 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 91903136 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 91903136 # Number of busy cycles +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26497334 # Number of memory references +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 92176625f..cab9a523d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 4d237e859..5503045c3 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:35:14 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 90176f56c..2aaa18b18 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2386222 # Simulator instruction rate (inst/s) -host_mem_usage 243572 # Number of bytes of host memory used -host_seconds 38.51 # Real time elapsed on the host -host_tick_rate 3083013039 # Simulator tick rate (ticks/s) +host_inst_rate 559604 # Simulator instruction rate (inst/s) +host_mem_usage 229724 # Number of bytes of host memory used +host_seconds 164.23 # Real time elapsed on the host +host_tick_rate 723015392 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 237480098 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 237480098 # Number of busy cycles +system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses +system.cpu.num_fp_insts 6862064 # number of float instructions +system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read +system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written +system.cpu.num_func_calls 2059216 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26497334 # Number of memory references +system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses +system.cpu.num_int_insts 79581109 # number of integer instructions +system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read +system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written +system.cpu.num_load_insts 19996208 # Number of load instructions +system.cpu.num_mem_refs 26497334 # number of memory refs +system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 95580ac45..f95eb4d89 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 832370508..46dd2c791 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 04:18:31 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:24 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index a8b50fb87..21ada4fbc 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 96216 # Simulator instruction rate (inst/s) -host_mem_usage 255460 # Number of bytes of host memory used -host_seconds 1920.75 # Real time elapsed on the host -host_tick_rate 78000522 # Simulator tick rate (ticks/s) +host_inst_rate 61621 # Simulator instruction rate (inst/s) +host_mem_usage 241964 # Number of bytes of host memory used +host_seconds 2999.07 # Real time elapsed on the host +host_tick_rate 49955205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 184806751 # Number of instructions simulated sim_seconds 0.149819 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 285162307 # Number of insts commited each cycle system.cpu.commit.COM:count 184806751 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 146860811 # Number of committed integer instructions. system.cpu.commit.COM:loads 29554611 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 42081439 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 299566319 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2799107 # number of floating regfile reads +system.cpu.fp_regfile_writes 2446180 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25129.997165 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 2461724 # system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1407561 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 457836856 # number of integer regfile reads +system.cpu.int_regfile_writes 195349958 # number of integer regfile writes system.cpu.ipc 0.616766 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.616766 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 299566319 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.711320 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1965612 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3923910 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1824312 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2255873 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 212345848 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 723342864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 197666637 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 240391153 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 220060942 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 213138842 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 3889323 # Nu system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 14988552 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 328971278 # number of misc regfile reads +system.cpu.misc_regfile_writes 4891827 # number of misc regfile writes system.cpu.numCycles 299638437 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 190277990 # Nu system.cpu.rename.RENAME:SquashCycles 14404012 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1750038 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 71145762 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 14827185 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 586253105 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 506291228 # The number of ROB reads +system.cpu.rob.rob_writes 457856948 # The number of ROB writes system.cpu.timesIdled 1363 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini index 9f4b7679d..283406dc2 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout index 4f3382663..c50fadfb0 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:22:41 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:35 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 45e4b8820..4a204d0cd 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2742393 # Simulator instruction rate (inst/s) -host_mem_usage 257424 # Number of bytes of host memory used -host_seconds 68.12 # Real time elapsed on the host -host_tick_rate 1499949275 # Simulator tick rate (ticks/s) +host_inst_rate 1012006 # Simulator instruction rate (inst/s) +host_mem_usage 232796 # Number of bytes of host memory used +host_seconds 184.60 # Real time elapsed on the host +host_tick_rate 553516772 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186818826 # Number of instructions simulated sim_seconds 0.102181 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 204361469 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 204361469 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 186818826 # Number of instructions executed -system.cpu.num_refs 42511846 # Number of memory references +system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses +system.cpu.num_int_insts 148453796 # number of integer instructions +system.cpu.num_int_register_reads 440904784 # number of times the integer registers were read +system.cpu.num_int_register_writes 179338779 # number of times the integer registers were written +system.cpu.num_load_insts 29867211 # Number of load instructions +system.cpu.num_mem_refs 42511846 # number of memory refs +system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini index c7e80818a..d150b1761 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr index eabe42249..83ecbdfc0 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,13 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout index 60b3eda0f..5cb7e11c7 100755 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:00:18 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2 +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt index b971df920..715b30669 100644 --- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 709254 # Simulator instruction rate (inst/s) -host_mem_usage 265144 # Number of bytes of host memory used -host_seconds 262.72 # Real time elapsed on the host -host_tick_rate 883179772 # Simulator tick rate (ticks/s) +host_inst_rate 504285 # Simulator instruction rate (inst/s) +host_mem_usage 240500 # Number of bytes of host memory used +host_seconds 369.50 # Real time elapsed on the host +host_tick_rate 627947562 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 186333855 # Number of instructions simulated sim_seconds 0.232028 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 464055342 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 464055342 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses +system.cpu.num_fp_insts 1752310 # number of float instructions +system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 186333855 # Number of instructions executed -system.cpu.num_refs 42511846 # Number of memory references +system.cpu.num_int_alu_accesses 148453796 # Number of integer alu accesses +system.cpu.num_int_insts 148453796 # number of integer instructions +system.cpu.num_int_register_reads 470866018 # number of times the integer registers were read +system.cpu.num_int_register_writes 179570637 # number of times the integer registers were written +system.cpu.num_load_insts 29867211 # Number of load instructions +system.cpu.num_mem_refs 42511846 # number of memory refs +system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 1b0da48ab..c1dd735f6 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf +executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index 30e9edddf..f4dfd8899 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:35:37 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:39 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index ec86f0831..5f3549812 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1979245 # Simulator instruction rate (inst/s) -host_mem_usage 190260 # Number of bytes of host memory used -host_seconds 97.74 # Real time elapsed on the host -host_tick_rate 989625806 # Simulator tick rate (ticks/s) +host_inst_rate 1142521 # Simulator instruction rate (inst/s) +host_mem_usage 224208 # Number of bytes of host memory used +host_seconds 169.31 # Real time elapsed on the host +host_tick_rate 571263026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 96722951500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 193445904 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references +system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read +system.cpu.num_int_register_writes 163703467 # number of times the integer registers were written +system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index dc0731aa6..c8439f7fb 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index a4fbf8115..a4abb12dd 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:03:51 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:19 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 46f688248..f02c69451 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 953366 # Simulator instruction rate (inst/s) -host_mem_usage 216056 # Number of bytes of host memory used -host_seconds 202.91 # Real time elapsed on the host -host_tick_rate 1333500122 # Simulator tick rate (ticks/s) +host_inst_rate 498703 # Simulator instruction rate (inst/s) +host_mem_usage 231920 # Number of bytes of host memory used +host_seconds 387.90 # Real time elapsed on the host +host_tick_rate 697549821 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270577 # Number of seconds simulated @@ -209,8 +209,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 541153920 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 541153920 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 193444769 # Number of instructions executed -system.cpu.num_refs 76733959 # Number of memory references +system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_int_register_reads 352386257 # number of times the integer registers were read +system.cpu.num_int_register_writes 163703466 # number of times the integer registers were written +system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733959 # number of memory refs +system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.workload.PROG:num_syscalls 401 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 64a0645d8..78a8cbd6c 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 4773ac641..e89403a2f 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index daddf87eb..58c1a1259 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118559 # Simulator instruction rate (inst/s) -host_mem_usage 239716 # Number of bytes of host memory used -host_seconds 1867.12 # Real time elapsed on the host -host_tick_rate 68319429 # Simulator tick rate (ticks/s) +host_inst_rate 87424 # Simulator instruction rate (inst/s) +host_mem_usage 240332 # Number of bytes of host memory used +host_seconds 2532.06 # Real time elapsed on the host +host_tick_rate 50378144 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.127561 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed +system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.COM:loads 56649590 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed @@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads +system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency @@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 5084805 # system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 614135119 # number of integer regfile reads +system.cpu.int_regfile_writes 252115460 # number of integer regfile writes system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued @@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ @@ -420,7 +435,11 @@ system.cpu.memDep0.conflictingLoads 21807942 # Nu system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads +system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.numCycles 255121086 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full @@ -433,10 +452,14 @@ system.cpu.rename.RENAME:RunCycles 180705413 # Nu system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 535181849 # The number of ROB reads +system.cpu.rob.rob_writes 594057529 # The number of ROB writes system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index 4d12813eb..adbeb371c 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index bf0a55710..3569c883b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:36:47 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 6fd518d60..da648dcbf 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 925477 # Simulator instruction rate (inst/s) -host_mem_usage 227168 # Number of bytes of host memory used -host_seconds 239.19 # Real time elapsed on the host -host_tick_rate 549329374 # Simulator tick rate (ticks/s) +host_inst_rate 777141 # Simulator instruction rate (inst/s) +host_mem_usage 230844 # Number of bytes of host memory used +host_seconds 284.84 # Real time elapsed on the host +host_tick_rate 461282227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 131393100000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 262786201 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 262786201 # Number of busy cycles +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_refs 77165306 # Number of memory references +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index bf2ab6302..2709fd0f4 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 8e7b2eaae..31ab1843b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a9095b1f2..ebc389a3a 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704710 # Simulator instruction rate (inst/s) -host_mem_usage 234884 # Number of bytes of host memory used -host_seconds 314.12 # Real time elapsed on the host -host_tick_rate 798933117 # Simulator tick rate (ticks/s) +host_inst_rate 446836 # Simulator instruction rate (inst/s) +host_mem_usage 238556 # Number of bytes of host memory used +host_seconds 495.40 # Real time elapsed on the host +host_tick_rate 506580174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 501921262 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 501921262 # Number of busy cycles +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_refs 77165306 # Number of memory references +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- |