51 files changed, 1010 insertions, 652 deletions

diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
deleted file mode 100644
index 87866a2a5..000000000
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
deleted file mode 100644
index 87866a2a5..000000000
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
deleted file mode 100644
index 87866a2a5..000000000
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
+++ /dev/null
@@ -1 +0,0 @@
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index fb3d24c55..5604f880f 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -7,43 +7,6 @@ max_tick=0
 output_file=cout
 progress_interval=0
 
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
 [system]
 type=System
 children=cpu membus physmem
@@ -388,11 +351,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
 egid=100
 env=
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 output=cout
@@ -414,14 +377,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
index e4ed95acf..a78c52d7f 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -26,11 +27,11 @@ responder_set=false
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
 system=system
 uid=100
 euid=100
@@ -366,51 +367,3 @@ clock=1000
 width=64
 responder_set=false
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index dfa1fbe0b..c77face31 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
 
 ---------- Begin Simulation Statistics ----------
 global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                     11837684                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  15197122                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                    1217                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                1998573                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               12917224                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     17533197                       # Number of BP lookups
-global.BPredUnit.usedRAS                      1687018                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  57997                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 178748                       # Number of bytes of host memory used
-host_seconds                                  1423.90                       # Real time elapsed on the host
-host_tick_rate                                  73521                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads           10104667                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores           3292311                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads              29530804                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores              9370879                       # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits                     11848811                       # Number of BTB hits
+global.BPredUnit.BTBLookups                  15227898                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                    1227                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect                2015952                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted               12943595                       # Number of conditional branches predicted
+global.BPredUnit.lookups                     17560137                       # Number of BP lookups
+global.BPredUnit.usedRAS                      1685355                       # Number of times the RAS was used to get a target.
+host_inst_rate                                 110871                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 184176                       # Number of bytes of host memory used
+host_seconds                                   759.26                       # Real time elapsed on the host
+host_tick_rate                                 138735                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads            9867030                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores           3328836                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads              29553768                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores              9396457                       # Number of stores inserted to the mem dependence unit.
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    82582323                       # Number of instructions simulated
+sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.000105                       # Number of seconds simulated
-sim_ticks                                   104686099                       # Number of ticks simulated
-system.cpu.commit.COM:branches               10071057                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           3175901                       # number cycles where commit BW limit reached
+sim_ticks                                   105335101                       # Number of ticks simulated
+system.cpu.commit.COM:branches               10240685                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           3300349                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
 system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples     65490840                      
+system.cpu.commit.COM:committed_per_cycle.samples     65617496                      
 system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0     32034998   4891.52%           
-                               1     13785472   2104.95%           
-                               2      8057025   1230.25%           
-                               3      3669149    560.25%           
-                               4      1988059    303.56%           
-                               5      1377349    210.31%           
-                               6       785420    119.93%           
-                               7       617467     94.28%           
-                               8      3175901    484.94%           
+                               0     32041205   4883.03%           
+                               1     13628356   2076.94%           
+                               2      7878182   1200.62%           
+                               3      3859920    588.25%           
+                               4      2040157    310.92%           
+                               5      1456623    221.99%           
+                               6       796888    121.44%           
+                               7       615816     93.85%           
+                               8      3300349    502.97%           
 system.cpu.commit.COM:committed_per_cycle.max_value            8                      
 system.cpu.commit.COM:committed_per_cycle.end_dist
 
-system.cpu.commit.COM:count                  90187947                       # Number of instructions committed
-system.cpu.commit.COM:loads                  19613586                       # Number of loads committed
+system.cpu.commit.COM:count                  91903055                       # Number of instructions committed
+system.cpu.commit.COM:loads                  20034413                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   25981086                       # Number of memory references committed
+system.cpu.commit.COM:refs                   26537108                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           1985168                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       90187947                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls             387                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        40679620                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    82582323                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              82582323                       # Number of Instructions Simulated
-system.cpu.cpi                               1.267657                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.267657                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           22673452                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  5439.841232                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  4838.693712                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               22672608                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        4591226                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000037                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  844                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits               351                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency      2385476                       # number of ReadReq MSHR miss cycles
+system.cpu.commit.branchMispredicts           2003468                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts        39205061                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
+system.cpu.cpi                               1.251312                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.251312                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses           23022109                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  5495.207331                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  4910.485944                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               23021236                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        4797316                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.000038                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                  873                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits               375                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency      2445422                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             493                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6365908                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  5074.130393                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  4849.051425                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6360739                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      26228180                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000812                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                5169                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits             3555                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency      7826369                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000254                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1614                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs  2811.600000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets  3114.692857                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               13779.471761                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs                 10                       # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets              700                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs        28116                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets      2180285                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_mshr_misses             498                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  4880.722363                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  4578.932720                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               6495178                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      28918280                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000911                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                5925                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits             4186                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency      7962764                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1739                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs  2807.125000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets  3125.260571                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs               13194.641931                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  8                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets              875                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs        22457                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets      2734603                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            29039360                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  5125.462498                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  4846.627907                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                29033347                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        30819406                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000207                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  6013                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits               3906                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     10211845                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000073                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2107                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            29523212                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  4959.634598                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  4652.742959                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                29516414                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency        33715596                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000230                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  6798                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits               4561                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency     10408186                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000076                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses             2237                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           29039360                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  5125.462498                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  4846.627907                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               29033347                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       30819406                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000207                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 6013                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits              3906                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     10211845                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000073                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2107                       # number of overall MSHR misses
+system.cpu.dcache.overall_accesses           29523212                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  4959.634598                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  4652.742959                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits               29516414                       # number of overall hits
+system.cpu.dcache.overall_miss_latency       33715596                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000230                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 6798                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits              4561                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency     10408186                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000076                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses            2237                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                    104                       # number of replacements
-system.cpu.dcache.sampled_refs                   2107                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                    158                       # number of replacements
+system.cpu.dcache.sampled_refs                   2237                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1404.053454                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 29033347                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1400.647488                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 29516414                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       75                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        2221252                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          13564                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       2815361                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       145659694                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          36080141                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           27108364                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         6243203                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          50032                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles          81084                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                    17533197                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  17509399                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      45531133                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                484323                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      150299775                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                 2040341                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.244419                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           17509399                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           13524702                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.095236                       # Number of inst fetches per cycle
+system.cpu.dcache.writebacks                      105                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles        2047370                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          12661                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       2829477                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       146297095                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          36266329                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           27223403                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         6075840                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts          45354                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles          80395                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                    17560137                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  17576948                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      45711428                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                479088                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      150837354                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                 2061309                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.244934                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           17576948                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           13534166                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        2.103924                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples            71734044                      
+system.cpu.fetch.rateDist.samples            71693337                      
 system.cpu.fetch.rateDist.min_value                 0                      
-                               0     43713095   6093.77%           
-                               1      2792314    389.26%           
-                               2      2129360    296.84%           
-                               3      3194083    445.27%           
-                               4      4028588    561.60%           
-                               5      1363321    190.05%           
-                               6      1870461    260.75%           
-                               7      1629807    227.20%           
-                               8     11013015   1535.26%           
+                               0     43559639   6075.83%           
+                               1      2788432    388.94%           
+                               2      2133609    297.60%           
+                               3      3200202    446.37%           
+                               4      4098889    571.73%           
+                               5      1363717    190.22%           
+                               6      1885995    263.06%           
+                               7      1651845    230.40%           
+                               8     11011009   1535.85%           
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses           17509399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3388.211547                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2494.269154                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               17495889                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       45774738                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000772                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                13510                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              3486                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     25002554                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_accesses           17576948                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  3407.568545                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2506.978423                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               17563424                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       46083957                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000769                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                13524                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              3467                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     25212682                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000572                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           10024                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets  3400.454545                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                1745.399940                       # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_mshr_misses           10057                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets  3513.269231                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                1746.387988                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets               22                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets               26                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets        74810                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets        91345                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            17509399                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3388.211547                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2494.269154                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                17495889                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        45774738                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000772                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 13510                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               3486                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25002554                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_accesses            17576948                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  3407.568545                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2506.978423                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                17563424                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        46083957                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000769                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 13524                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               3467                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     25212682                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000572                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            10024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses            10057                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           17509399                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3388.211547                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2494.269154                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               17495889                       # number of overall hits
-system.cpu.icache.overall_miss_latency       45774738                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000772                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                13510                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              3486                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25002554                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_accesses           17576948                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  3407.568545                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2506.978423                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits               17563424                       # number of overall hits
+system.cpu.icache.overall_miss_latency       46083957                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000769                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                13524                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              3467                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     25212682                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000572                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           10024                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses           10057                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                   8115                       # number of replacements
-system.cpu.icache.sampled_refs                  10024                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   8145                       # number of replacements
+system.cpu.icache.sampled_refs                  10057                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1481.631027                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 17495889                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1487.085502                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 17563424                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        32952056                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 12456785                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      11559797                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.365191                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     30958353                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    7006627                       # Number of stores executed
+system.cpu.idleCycles                        33641765                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 12581618                       # Number of branches executed
+system.cpu.iew.EXEC:nop                      11617565                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.388001                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     31473535                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    7134398                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  86914579                       # num instructions consuming a value
-system.cpu.iew.WB:count                      96291361                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.729319                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  88408054                       # num instructions consuming a value
+system.cpu.iew.WB:count                      97920299                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.731090                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  63388475                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.342338                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       96947832                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              2153450                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                  156060                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              29530804                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                437                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           2057217                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              9370879                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           130866464                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              23951726                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2095770                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              97930658                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  43929                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  64634219                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.365821                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       98494929                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              2154192                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  104376                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              29553768                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                436                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           2191495                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              9396457                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           131107086                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              24339137                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2193063                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              99510422                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  16363                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   720                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                6243203                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 62133                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads         9874                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked        40553                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          855538                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         3321                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents                   879                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                6075840                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 34734                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads         9915                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked        36009                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          941599                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         3004                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        18493                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         9874                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      9917218                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      3003379                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          18493                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      1143572                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        1009878                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.788857                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.788857                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0               100026428                       # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation        23070                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads         9915                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      9519355                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      2893762                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          23070                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       196104                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        1958088                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.799161                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.799161                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0               101703485                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                           (null)            7      0.00%            # Type of FU issued
-                          IntAlu     61666427     61.65%            # Type of FU issued
-                         IntMult       468908      0.47%            # Type of FU issued
+                          IntAlu     62578225     61.53%            # Type of FU issued
+                         IntMult       472394      0.46%            # Type of FU issued
                           IntDiv            0      0.00%            # Type of FU issued
-                        FloatAdd      2704055      2.70%            # Type of FU issued
-                        FloatCmp       112834      0.11%            # Type of FU issued
-                        FloatCvt      2307257      2.31%            # Type of FU issued
-                       FloatMult       295394      0.30%            # Type of FU issued
-                        FloatDiv       735688      0.74%            # Type of FU issued
-                       FloatSqrt          122      0.00%            # Type of FU issued
-                         MemRead     24586382     24.58%            # Type of FU issued
-                        MemWrite      7149354      7.15%            # Type of FU issued
+                        FloatAdd      2776755      2.73%            # Type of FU issued
+                        FloatCmp       115486      0.11%            # Type of FU issued
+                        FloatCvt      2376016      2.34%            # Type of FU issued
+                       FloatMult       302348      0.30%            # Type of FU issued
+                        FloatDiv       754954      0.74%            # Type of FU issued
+                       FloatSqrt          321      0.00%            # Type of FU issued
+                         MemRead     25019338     24.60%            # Type of FU issued
+                        MemWrite      7307641      7.19%            # Type of FU issued
                        IprAccess            0      0.00%            # Type of FU issued
                     InstPrefetch            0      0.00%            # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt               1620744                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.016203                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt               1392706                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.013694                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full.start_dist
-                          (null)            0      0.00%            # attempts to use FU when none available
-                          IntAlu       195067     12.04%            # attempts to use FU when none available
-                         IntMult            0      0.00%            # attempts to use FU when none available
-                          IntDiv            0      0.00%            # attempts to use FU when none available
-                        FloatAdd         1678      0.10%            # attempts to use FU when none available
-                        FloatCmp          197      0.01%            # attempts to use FU when none available
-                        FloatCvt         4552      0.28%            # attempts to use FU when none available
-                       FloatMult         2392      0.15%            # attempts to use FU when none available
-                        FloatDiv       951463     58.71%            # attempts to use FU when none available
-                       FloatSqrt            0      0.00%            # attempts to use FU when none available
-                         MemRead       401417     24.77%            # attempts to use FU when none available
-                        MemWrite        63978      3.95%            # attempts to use FU when none available
-                       IprAccess            0      0.00%            # attempts to use FU when none available
-                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+(null)                                              0      0.00%            # attempts to use FU when none available
+IntAlu                                         193189     13.87%            # attempts to use FU when none available
+IntMult                                             0      0.00%            # attempts to use FU when none available
+IntDiv                                              0      0.00%            # attempts to use FU when none available
+FloatAdd                                         1883      0.14%            # attempts to use FU when none available
+FloatCmp                                           96      0.01%            # attempts to use FU when none available
+FloatCvt                                         2836      0.20%            # attempts to use FU when none available
+FloatMult                                        2464      0.18%            # attempts to use FU when none available
+FloatDiv                                       659899     47.38%            # attempts to use FU when none available
+FloatSqrt                                           0      0.00%            # attempts to use FU when none available
+MemRead                                        465101     33.40%            # attempts to use FU when none available
+MemWrite                                        67238      4.83%            # attempts to use FU when none available
+IprAccess                                           0      0.00%            # attempts to use FU when none available
+InstPrefetch                                        0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
 system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples     71734044                      
+system.cpu.iq.ISSUE:issued_per_cycle.samples     71693337                      
 system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     28631398   3991.33%           
-                               1     15448994   2153.65%           
-                               2     12333631   1719.36%           
-                               3      7046540    982.31%           
-                               4      4503539    627.81%           
-                               5      2295007    319.93%           
-                               6      1113179    155.18%           
-                               7       291761     40.67%           
-                               8        69995      9.76%           
+                               0     27977053   3902.32%           
+                               1     15408153   2149.18%           
+                               2     12854527   1792.99%           
+                               3      7056557    984.27%           
+                               4      4494209    626.87%           
+                               5      2427532    338.60%           
+                               6      1097338    153.06%           
+                               7       305661     42.63%           
+                               8        72307     10.09%           
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.394407                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                  119306230                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 100026428                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                 437                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        35838359                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            150449                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             50                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     30462150                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses             12131                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  3919.717352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2067.943230                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  7146                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      19539791                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.410931                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4985                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     10308697                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.410931                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4985                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses           75                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits           75                       # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.448546                       # Average number of references to valid blocks.
+system.cpu.iq.ISSUE:rate                     1.418590                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                  119489085                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 101703485                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                 436                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        34413373                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            132312                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     28441004                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses             12293                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  3855.809345                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2071.040418                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                  7221                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      19556665                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.412593                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                5072                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     10504317                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.412593                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           5072                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses             105                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 105                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  1.444401                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              12131                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  3919.717352                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  2067.943230                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   7146                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       19539791                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.410931                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4985                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses              12293                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  3855.809345                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  2071.040418                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                   7221                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency       19556665                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.412593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 5072                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     10308697                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.410931                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4985                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency     10504317                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.412593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            5072                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses             12206                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  3919.717352                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  2067.943230                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  7221                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      19539791                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.408406                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4985                       # number of overall misses
+system.cpu.l2cache.overall_accesses             12398                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  3855.809345                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  2071.040418                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                  7326                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency      19556665                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.409098                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                5072                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     10308697                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.408406                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4985                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency     10504317                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.409098                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           5072                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -383,31 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4985                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  5072                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3244.539242                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    7221                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3261.872945                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    7326                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                         71734044                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles           969328                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       67122956                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          411688                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          37058676                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         742595                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents            109                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      181728449                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       141044897                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    103457127                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           26196123                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         6243203                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1187915                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          36334171                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles        78799                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          513                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            2731208                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          502                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                           10186                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             387                       # Number of system calls
+system.cpu.numCycles                         71693337                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles           812700                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents          369396                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          37208342                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents         772307                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents            122                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      182866276                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       141908898                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    104156212                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           26334995                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         6075840                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        1200845                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          35728851                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles        60615                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts          555                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts            2896644                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts          544                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                           10380                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
new file mode 100644
index 000000000..eb1796ead
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
@@ -0,0 +1,2 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index fbf8dd865..789f77815 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -7,21 +7,6 @@ max_tick=0
 output_file=cout
 progress_interval=0
 
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
 [serialize]
 count=10
 cycle=0
@@ -74,7 +59,7 @@ icache_port=system.membus.port[1]
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
 egid=100
 env=
 euid=100
@@ -100,14 +85,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
index 5375d2a8f..b4087eb1c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
 system=system
 uid=100
 euid=100
@@ -57,15 +58,6 @@ function_trace=false
 function_trace_start=0
 simulate_stalls=false
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
 [stats]
 descriptions=true
 project_name=test
@@ -83,25 +75,6 @@ dump_cycle=0
 dump_period=0
 ignore_events=
 
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
 [statsreset]
 reset_cycle=0
 
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
index e5e0a4991..2cd5a06bf 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,18 +1,18 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 827042                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 146736                       # Number of bytes of host memory used
-host_seconds                                   111.12                       # Real time elapsed on the host
-host_tick_rate                                 827039                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1013473                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 151596                       # Number of bytes of host memory used
+host_seconds                                    90.68                       # Real time elapsed on the host
+host_tick_rate                                1013469                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91900700                       # Number of instructions simulated
+sim_insts                                    91903057                       # Number of instructions simulated
 sim_seconds                                  0.000092                       # Number of seconds simulated
-sim_ticks                                    91900699                       # Number of ticks simulated
+sim_ticks                                    91903056                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         91900700                       # number of cpu cycles simulated
-system.cpu.num_insts                         91900700                       # Number of instructions executed
-system.cpu.num_refs                          26536244                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls             387                       # Number of system calls
+system.cpu.numCycles                         91903057                       # number of cpu cycles simulated
+system.cpu.num_insts                         91903057                       # Number of instructions executed
+system.cpu.num_refs                          26537109                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
new file mode 100644
index 000000000..eb1796ead
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
@@ -0,0 +1,2 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 9f6151e4d..e2265235e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -7,21 +7,6 @@ max_tick=0
 output_file=cout
 progress_interval=0
 
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
 [serialize]
 count=10
 cycle=0
@@ -197,7 +182,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
 egid=100
 env=
 euid=100
@@ -223,14 +208,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
index c27975bcb..fcf06c7db 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
 system=system
 uid=100
 euid=100
@@ -178,15 +179,6 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
 [stats]
 descriptions=true
 project_name=test
@@ -204,25 +196,6 @@ dump_cycle=0
 dump_period=0
 ignore_events=
 
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
 [statsreset]
 reset_cycle=0
 
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index 3926b2de9..5cdae9c4a 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 460435                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 178124                       # Number of bytes of host memory used
-host_seconds                                   199.60                       # Real time elapsed on the host
-host_tick_rate                                 765898                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 607322                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 157212                       # Number of bytes of host memory used
+host_seconds                                   151.33                       # Real time elapsed on the host
+host_tick_rate                                1013960                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    91900700                       # Number of instructions simulated
+sim_insts                                    91903057                       # Number of instructions simulated
 sim_seconds                                  0.000153                       # Number of seconds simulated
-sim_ticks                                   152870012                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses           19995627                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3765.212314                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2765.212314                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               19995156                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        1773415                       # number of ReadReq miss cycles
+sim_ticks                                   153438012                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  3701.356540                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2701.356540                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               19995724                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        1754443                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  471                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1302415                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                  474                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      1280443                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             471                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6500813                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3867.178372                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2867.178372                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6499204                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       6222290                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000248                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1609                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency      4613290                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000248                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1609                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses             474                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  3869.070366                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2869.070366                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency       6763135                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency      5015135                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               12737.673077                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               11923.977948                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            26496440                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3844.088942                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2844.088942                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26494360                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         7995705                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000079                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2080                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  3833.293429                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2833.293429                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26495079                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         8517578                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  2222                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      5915705                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000079                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2080                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency      6295578                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses             2222                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           26496440                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3844.088942                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2844.088942                       # average overall mshr miss latency
+system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  3833.293429                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2833.293429                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26494360                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        7995705                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000079                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2080                       # number of overall misses
+system.cpu.dcache.overall_hits               26495079                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        8517578                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 2222                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      5915705                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000079                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2080                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency      6295578                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses            2222                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                    103                       # number of replacements
-system.cpu.dcache.sampled_refs                   2080                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                    157                       # number of replacements
+system.cpu.dcache.sampled_refs                   2222                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1399.324024                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26494360                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1398.130089                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26495079                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       74                       # number of writebacks
-system.cpu.icache.ReadReq_accesses           91900701                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3116.205529                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2116.205529                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               91892201                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       26487747                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000092                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 8500                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     17987747                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000092                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            8500                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks                      104                       # number of writebacks
+system.cpu.icache.ReadReq_accesses           91903058                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  3117.603760                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2117.603760                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               91894548                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       26530808                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000093                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 8510                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency     18020808                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000093                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses            8510                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               10810.847176                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               10798.419271                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            91900701                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3116.205529                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2116.205529                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                91892201                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        26487747                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000092                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  8500                       # number of demand (read+write) misses
+system.cpu.icache.demand_accesses            91903058                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  3117.603760                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2117.603760                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                91894548                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        26530808                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000093                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  8510                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     17987747                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000092                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             8500                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency     18020808                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000093                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses             8510                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           91900701                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3116.205529                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2116.205529                       # average overall mshr miss latency
+system.cpu.icache.overall_accesses           91903058                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  3117.603760                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2117.603760                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               91892201                       # number of overall hits
-system.cpu.icache.overall_miss_latency       26487747                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000092                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 8500                       # number of overall misses
+system.cpu.icache.overall_hits               91894548                       # number of overall hits
+system.cpu.icache.overall_miss_latency       26530808                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000093                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 8510                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     17987747                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000092                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            8500                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency     18020808                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000093                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses            8510                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                   6677                       # number of replacements
-system.cpu.icache.sampled_refs                   8500                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   6681                       # number of replacements
+system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1370.015418                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 91892201                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1374.520503                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 91894548                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses             10580                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2883.751500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1878.799057                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  5912                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      13461352                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.441210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4668                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      8770234                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.441210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4668                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses           74                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits           74                       # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.ReadReq_accesses             10732                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  2892.483207                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1885.503778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                  5968                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      13779790                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.443906                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                4764                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      8982540                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.443906                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           4764                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.282348                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.274559                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              10580                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2883.751500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1878.799057                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   5912                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       13461352                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.441210                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4668                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses              10732                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  2892.483207                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1885.503778                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                   5968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency       13779790                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.443906                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4764                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency      8770234                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.441210                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4668                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency      8982540                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.443906                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4764                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses             10654                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2883.751500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1878.799057                       # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses             10836                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  2892.483207                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1885.503778                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  5986                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      13461352                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.438145                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4668                       # number of overall misses
+system.cpu.l2cache.overall_hits                  6072                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency      13779790                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.439646                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4764                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      8770234                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.438145                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4668                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency      8982540                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.439646                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4764                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4668                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4764                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3056.777484                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    5986                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3073.845977                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    6072                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        152870012                       # number of cpu cycles simulated
-system.cpu.num_insts                         91900700                       # Number of instructions executed
-system.cpu.num_refs                          26536244                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls             387                       # Number of system calls
+system.cpu.numCycles                        153438012                       # number of cpu cycles simulated
+system.cpu.num_insts                         91903057                       # Number of instructions executed
+system.cpu.num_refs                          26537109                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
new file mode 100644
index 000000000..eb1796ead
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
@@ -0,0 +1,2 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index f32f0a972..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..2a1613fa1
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,64 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
new file mode 100644
index 000000000..d24c09793
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
@@ -0,0 +1,57 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+input=cin
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..45fd6b479
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 676464                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 149916                       # Number of bytes of host memory used
+host_seconds                                   285.95                       # Real time elapsed on the host
+host_tick_rate                                 676463                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                   193435973                       # Number of instructions simulated
+sim_seconds                                  0.000193                       # Number of seconds simulated
+sim_ticks                                   193435972                       # Number of ticks simulated
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                        193435973                       # number of cpu cycles simulated
+system.cpu.num_insts                        193435973                       # Number of instructions executed
+system.cpu.num_refs                          76732959                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls             396                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
new file mode 100644
index 000000000..94662b6e8
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
@@ -0,0 +1,8 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x11e394 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
+warn: Ignoring request to flush register windows.
+warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
new file mode 100644
index 000000000..7c0e5ba5f
--- /dev/null
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -0,0 +1,28 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 12 2007 16:53:49
+M5 started Mon Mar 12 17:37:07 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 193435972 because target called exit()