diff options
Diffstat (limited to 'tests/long/70.twolf/ref')
17 files changed, 426 insertions, 428 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 04020c643..72c4312d9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index 50da468a0..e3bf50f10 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 8e2806190..8dcfd61cf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 14247678 # Number of BTB hits -global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted -global.BPredUnit.lookups 20998495 # Number of BP lookups -global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target. -host_inst_rate 58248 # Simulator instruction rate (inst/s) -host_mem_usage 156992 # Number of bytes of host memory used -host_seconds 1445.19 # Real time elapsed on the host -host_tick_rate 23712867 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11874522 # Number of BTB hits +global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted +global.BPredUnit.lookups 17824174 # Number of BP lookups +global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target. +host_inst_rate 74830 # Simulator instruction rate (inst/s) +host_mem_usage 156844 # Number of bytes of host memory used +host_seconds 1124.95 # Real time elapsed on the host +host_tick_rate 39347975 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.034270 # Number of seconds simulated -sim_ticks 34269677000 # Number of ticks simulated +sim_seconds 0.044264 # Number of seconds simulated +sim_ticks 44264420500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 59572652 +system.cpu.commit.COM:committed_per_cycle.samples 81602250 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 25280039 4243.56% - 1 15284536 2565.70% - 2 7326530 1229.85% - 3 3334393 559.72% - 4 2152142 361.26% - 5 1242273 208.53% - 6 890288 149.45% - 7 698989 117.33% - 8 3363462 564.60% + 0 44887304 5500.74% + 1 17052684 2089.73% + 2 8186225 1003.19% + 3 3991011 489.08% + 4 1764745 216.26% + 5 1325913 162.48% + 6 892255 109.34% + 7 554091 67.90% + 8 2948022 361.27% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency -system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 30105743 # number of overall hits -system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8254 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29540842 # number of overall hits +system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7956 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 162 # number of replacements -system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 163 # number of replacements +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use -system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use +system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched -system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched +system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 68539351 +system.cpu.fetch.rateDist.samples 88528924 system.cpu.fetch.rateDist.min_value 0 - 0 37270886 5437.88% - 1 3420236 499.02% - 2 1457458 212.65% - 3 2151808 313.95% - 4 4198050 612.50% - 5 1495508 218.20% - 6 1665097 242.94% - 7 1343985 196.09% - 8 15536323 2266.77% + 0 61853767 6986.84% + 1 2838595 320.64% + 2 1299355 146.77% + 3 1865057 210.67% + 4 3537974 399.64% + 5 1231942 139.16% + 6 1400771 158.23% + 7 1171977 132.38% + 8 13329486 1505.66% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency -system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses -system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency +system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses +system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency +system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20196480 # number of overall hits -system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses -system.cpu.icache.overall_misses 10349 # number of overall misses -system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses +system.cpu.icache.overall_hits 18006143 # number of overall hits +system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses +system.cpu.icache.overall_misses 10122 # number of overall misses +system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8192 # number of replacements -system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks. +system.cpu.icache.replacements 7904 # number of replacements +system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use -system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use +system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13347594 # Number of branches executed -system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate -system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7352116 # Number of stores executed +system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12543861 # Number of branches executed +system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate +system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7145648 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value -system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back +system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value +system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 68574976 # num instructions producing a value -system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle -system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 63859133 # num instructions producing a value +system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle +system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 66598699 62.21% # Type of FU issued - IntMult 478232 0.45% # Type of FU issued + IntAlu 62609480 61.69% # Type of FU issued + IntMult 467679 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2814666 2.63% # Type of FU issued - FloatCmp 115604 0.11% # Type of FU issued - FloatCvt 2391391 2.23% # Type of FU issued - FloatMult 308778 0.29% # Type of FU issued - FloatDiv 755076 0.71% # Type of FU issued - FloatSqrt 324 0.00% # Type of FU issued - MemRead 26034990 24.32% # Type of FU issued - MemWrite 7553301 7.06% # Type of FU issued + FloatAdd 2780950 2.74% # Type of FU issued + FloatCmp 115557 0.11% # Type of FU issued + FloatCvt 2364134 2.33% # Type of FU issued + FloatMult 305451 0.30% # Type of FU issued + FloatDiv 755050 0.74% # Type of FU issued + FloatSqrt 320 0.00% # Type of FU issued + MemRead 24826231 24.46% # Type of FU issued + MemWrite 7259828 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 352978 15.81% # attempts to use FU when none available + IntAlu 236478 13.59% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 856 0.04% # attempts to use FU when none available - FloatCmp 8 0.00% # attempts to use FU when none available - FloatCvt 3654 0.16% # attempts to use FU when none available - FloatMult 2325 0.10% # attempts to use FU when none available - FloatDiv 987087 44.20% # attempts to use FU when none available + FloatAdd 1 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 223 0.01% # attempts to use FU when none available + FloatMult 1629 0.09% # attempts to use FU when none available + FloatDiv 705159 40.54% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 766963 34.34% # attempts to use FU when none available - MemWrite 119376 5.35% # attempts to use FU when none available + MemRead 710061 40.82% # attempts to use FU when none available + MemWrite 85961 4.94% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351 +system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 25564605 3729.92% - 1 14833050 2164.17% - 2 10859904 1584.48% - 3 6945297 1013.33% - 4 5154135 752.00% - 5 2881350 420.39% - 6 1567848 228.75% - 7 633355 92.41% - 8 99807 14.56% + 0 43673541 4933.25% + 1 18286123 2065.55% + 2 11155754 1260.13% + 3 6962814 786.50% + 4 4628513 522.82% + 5 2073707 234.24% + 6 1255435 141.81% + 7 360879 40.76% + 8 132158 14.93% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate -system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate +system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7342 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5124 # number of overall misses +system.cpu.l2cache.overall_hits 7082 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5088 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 68539351 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking +system.cpu.numCycles 88528924 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed +system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 24a71167b..3cb797e6a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index 296e0472f..47defa937 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index b11bd8cad..acfa7c9dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 754988 # Simulator instruction rate (inst/s) -host_mem_usage 150624 # Number of bytes of host memory used -host_seconds 121.73 # Real time elapsed on the host -host_tick_rate 377492666 # Simulator tick rate (ticks/s) +host_inst_rate 935813 # Simulator instruction rate (inst/s) +host_mem_usage 150648 # Number of bytes of host memory used +host_seconds 98.21 # Real time elapsed on the host +host_tick_rate 467904361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cd04983c0..7edcc9166 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index 3089af658..3ed492885 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index b45fb965e..9f5824722 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 335846 # Simulator instruction rate (inst/s) -host_mem_usage 156240 # Number of bytes of host memory used -host_seconds 273.71 # Real time elapsed on the host -host_tick_rate 216396349 # Simulator tick rate (ticks/s) +host_inst_rate 651405 # Simulator instruction rate (inst/s) +host_mem_usage 156232 # Number of bytes of host memory used +host_seconds 141.08 # Real time elapsed on the host +host_tick_rate 840119018 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.059229 # Number of seconds simulated -sim_ticks 59229023000 # Number of ticks simulated +sim_seconds 0.118528 # Number of seconds simulated +sim_ticks 118527938000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26495079 # number of overall hits -system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894548 # number of overall hits -system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 6072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59229023000 # number of cpu cycles simulated +system.cpu.numCycles 118527938000 # number of cpu cycles simulated system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_refs 26537109 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 5aa5f86fe..3dcf027c2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out index f078d661c..d448056f4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 5532c6dba..c41d3b35f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 668374 # Simulator instruction rate (inst/s) -host_mem_usage 150556 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host -host_tick_rate 334186387 # Simulator tick rate (ticks/s) +host_inst_rate 673586 # Simulator instruction rate (inst/s) +host_mem_usage 150548 # Number of bytes of host memory used +host_seconds 287.17 # Real time elapsed on the host +host_tick_rate 336792536 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated sim_seconds 0.096718 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 2cdcc205c..f878587c3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,8 +18,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:03:50 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:48:51 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index ec76ab996..2a87cb78d 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out index dbecb5fa5..f79151c21 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 2c6679b72..0f4d2b473 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 490451 # Simulator instruction rate (inst/s) -host_mem_usage 156012 # Number of bytes of host memory used -host_seconds 394.40 # Real time elapsed on the host -host_tick_rate 342594746 # Simulator tick rate (ticks/s) +host_inst_rate 500598 # Simulator instruction rate (inst/s) +host_mem_usage 156000 # Number of bytes of host memory used +host_seconds 386.41 # Real time elapsed on the host +host_tick_rate 699597163 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.135121 # Number of seconds simulated -sim_ticks 135120940500 # Number of ticks simulated +sim_seconds 0.270332 # Number of seconds simulated +sim_ticks 270331639000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1584 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5167 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 135120940500 # number of cpu cycles simulated +system.cpu.numCycles 270331639000 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index eb4e3bbfa..316a2c0d3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:08:41 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:53:38 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 135120940500 because target called exit() +Exiting @ tick 270331639000 because target called exit() |