diff options
Diffstat (limited to 'tests/long/70.twolf/ref')
4 files changed, 53 insertions, 51 deletions
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 5a804eb57..b27d83682 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:56:10 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:33:08 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270578573000 because target called exit() +122 123 124 Exiting @ tick 270578335000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 571ff6af8..f73a0dcbf 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1319897 # Simulator instruction rate (inst/s) -host_mem_usage 209760 # Number of bytes of host memory used -host_seconds 146.56 # Real time elapsed on the host -host_tick_rate 1846186883 # Simulator tick rate (ticks/s) +host_inst_rate 732316 # Simulator instruction rate (inst/s) +host_mem_usage 209324 # Number of bytes of host memory used +host_seconds 264.15 # Real time elapsed on the host +host_tick_rate 1024317022 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270579 # Number of seconds simulated -sim_ticks 270578573000 # Number of ticks simulated +sim_seconds 0.270578 # Number of seconds simulated +sim_ticks 270578335000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # ms system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits +system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193433499 # number of overall hits +system.cpu.icache.overall_hits 193433261 # number of overall hits system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses system.cpu.icache.overall_misses 12288 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use -system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use +system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541157146 # number of cpu cycles simulated +system.cpu.numCycles 541156670 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 4e1b45a86..2a43627aa 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:57:42 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:58:47 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav @@ -29,4 +29,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469588000 because target called exit() +122 123 124 Exiting @ tick 250945484000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a85a5c18f..3d7cbb069 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 565225 # Simulator instruction rate (inst/s) -host_mem_usage 211860 # Number of bytes of host memory used -host_seconds 386.74 # Real time elapsed on the host -host_tick_rate 872598896 # Simulator tick rate (ticks/s) +host_inst_rate 660588 # Simulator instruction rate (inst/s) +host_mem_usage 211972 # Number of bytes of host memory used +host_seconds 330.91 # Real time elapsed on the host +host_tick_rate 758349031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated -sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469588000 # Number of ticks simulated +sim_seconds 0.250945 # Number of seconds simulated +sim_ticks 250945484000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits +system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013777 # number of overall hits +system.cpu.icache.overall_hits 173489673 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use -system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use +system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939176 # number of cpu cycles simulated +system.cpu.numCycles 501890968 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |