diff options
Diffstat (limited to 'tests/long/70.twolf/ref')
9 files changed, 1134 insertions, 1129 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9b349a51c..cbca14c5b 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index cae861e0e..43a475337 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 19:50:53 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:49:49 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 33574995000 because target called exit() +122 123 124 Exiting @ tick 30278595500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 9b4ccbc94..08d328376 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033575 # Number of seconds simulated -sim_ticks 33574995000 # Number of ticks simulated +sim_seconds 0.030279 # Number of seconds simulated +sim_ticks 30278595500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75399 # Simulator instruction rate (inst/s) -host_tick_rate 30072740 # Simulator tick rate (ticks/s) -host_mem_usage 250632 # Number of bytes of host memory used -host_seconds 1116.46 # Real time elapsed on the host +host_inst_rate 116969 # Simulator instruction rate (inst/s) +host_tick_rate 42072708 # Simulator tick rate (ticks/s) +host_mem_usage 256296 # Number of bytes of host memory used +host_seconds 719.67 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25910068 # DTB read hits -system.cpu.dtb.read_misses 487884 # DTB read misses +system.cpu.dtb.read_hits 25688278 # DTB read hits +system.cpu.dtb.read_misses 550762 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26397952 # DTB read accesses -system.cpu.dtb.write_hits 7442430 # DTB write hits -system.cpu.dtb.write_misses 947 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7443377 # DTB write accesses -system.cpu.dtb.data_hits 33352498 # DTB hits -system.cpu.dtb.data_misses 488831 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 33841329 # DTB accesses -system.cpu.itb.fetch_hits 20391081 # ITB hits +system.cpu.dtb.read_accesses 26239040 # DTB read accesses +system.cpu.dtb.write_hits 7360758 # DTB write hits +system.cpu.dtb.write_misses 1044 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7361802 # DTB write accesses +system.cpu.dtb.data_hits 33049036 # DTB hits +system.cpu.dtb.data_misses 551806 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 33600842 # DTB accesses +system.cpu.itb.fetch_hits 19370237 # ITB hits system.cpu.itb.fetch_misses 82 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 20391163 # ITB accesses +system.cpu.itb.fetch_accesses 19370319 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 67149991 # number of cpu cycles simulated +system.cpu.numCycles 60557192 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20043424 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14890335 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1886616 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 16546187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12995160 # Number of BTB hits +system.cpu.BPredUnit.lookups 18972162 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 14043194 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1908534 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15684343 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12020738 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1876944 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2472 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 21676746 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 172437485 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20043424 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14872104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 31892042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10307497 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5295116 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1817403 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2435 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 20660360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 162109118 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18972162 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13838141 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 29871214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8831306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3272537 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 20391081 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 650323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 67056836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.571512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.236226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 19370237 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 684277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60463700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.681098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.259568 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 35164794 52.44% 52.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3176485 4.74% 57.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2538345 3.79% 60.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3535941 5.27% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4282691 6.39% 72.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1574198 2.35% 74.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1997484 2.98% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1705355 2.54% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 13081543 19.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 30592486 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2950542 4.88% 55.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2105012 3.48% 58.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3386904 5.60% 64.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4238557 7.01% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1492876 2.47% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1782148 2.95% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1645056 2.72% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12270119 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 67056836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298487 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.567945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23902898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4218142 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 29787412 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 970752 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8177632 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3156419 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 166261756 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43031 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8177632 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25731687 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1160543 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 28902105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3078846 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 159343297 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 60463700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.313293 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.676959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22547787 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2537266 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 28115662 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 618580 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6644405 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2987075 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13654 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 155918946 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42842 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6644405 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24245198 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 523469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6031 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 27028766 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2015831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148832808 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 846266 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1904805 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 117303281 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 206166674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 193984489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 12182185 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 266593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1498062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 109279851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 192445710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 181748286 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10697424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48875920 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 516 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8753950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33541628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10395963 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7223070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2102878 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 134779237 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107642256 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 461690 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 49489496 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42823427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 67056836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.605239 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.754849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 40852490 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 518 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 515 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6036784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30729381 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9521294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2640558 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 881343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 123679327 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 494 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105899114 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 512588 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 38384232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30395152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 105 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60463700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.751449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.825920 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24956395 37.22% 37.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14036514 20.93% 58.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10136000 15.12% 73.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7177120 10.70% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5400162 8.05% 92.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2788229 4.16% 96.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1798139 2.68% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 642461 0.96% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121816 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21057299 34.83% 34.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11707934 19.36% 54.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9587960 15.86% 70.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6925941 11.45% 81.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5557420 9.19% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2847009 4.71% 95.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1835835 3.04% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796714 1.32% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 147588 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 67056836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60463700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 201993 12.31% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 250 0.02% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6175 0.38% 12.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5518 0.34% 13.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 850319 51.81% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 486670 29.65% 94.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 90238 5.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186761 11.23% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 209 0.01% 11.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6487 0.39% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3444 0.21% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 845716 50.84% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 517920 31.13% 93.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 103033 6.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 65718321 61.05% 61.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491419 0.46% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2837753 2.64% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114927 0.11% 64.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2460943 2.29% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308030 0.29% 66.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 776022 0.72% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27323056 25.38% 92.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7611460 7.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 64090689 60.52% 60.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 486042 0.46% 60.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2799885 2.64% 63.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114989 0.11% 63.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2411237 2.28% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311681 0.29% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763573 0.72% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27425152 25.90% 92.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7495540 7.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107642256 # Type of FU issued -system.cpu.iq.rate 1.603012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1641163 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 268833280 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 171996090 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 95630473 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15610921 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12638151 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7243335 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 101046338 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8237074 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1306070 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105899114 # Type of FU issued +system.cpu.iq.rate 1.748745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1663570 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015709 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 259207602 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 152594620 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93309235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15230484 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9878183 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7072078 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 99520074 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8042603 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1240194 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13545430 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9202 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 431066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3894860 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10733183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14770 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 472388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3020191 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10948 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10319 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8177632 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205335 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 131722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 147421220 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 680146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33541628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10395963 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 498 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 98656 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 431066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1771181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338775 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2109956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105130467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26398523 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2511789 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6644405 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16385 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 135563884 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 881728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30729381 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9521294 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 494 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 472388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1792269 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 350241 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2142510 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 103141866 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26239584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2757248 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12641484 # number of nop insts executed -system.cpu.iew.exec_refs 33841971 # number of memory reference insts executed -system.cpu.iew.exec_branches 13292827 # Number of branches executed -system.cpu.iew.exec_stores 7443448 # Number of stores executed -system.cpu.iew.exec_rate 1.565607 # Inst execution rate -system.cpu.iew.wb_sent 103975635 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102873808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 69418102 # num instructions producing a value -system.cpu.iew.wb_consumers 96250402 # num instructions consuming a value +system.cpu.iew.exec_nop 11884063 # number of nop insts executed +system.cpu.iew.exec_refs 33601488 # number of memory reference insts executed +system.cpu.iew.exec_branches 12972684 # Number of branches executed +system.cpu.iew.exec_stores 7361904 # Number of stores executed +system.cpu.iew.exec_rate 1.703214 # Inst execution rate +system.cpu.iew.wb_sent 101639951 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 100381313 # cumulative count of insts written-back +system.cpu.iew.wb_producers 68069676 # num instructions producing a value +system.cpu.iew.wb_consumers 93955815 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.532000 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721224 # average fanout of values written-back +system.cpu.iew.wb_rate 1.657628 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724486 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 55519927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43662883 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1873181 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 58879204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.560875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.342568 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1895215 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 53819295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.707623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.466902 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 27960283 47.49% 47.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13480171 22.89% 70.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5538232 9.41% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2736120 4.65% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1795830 3.05% 87.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1555437 2.64% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 775440 1.32% 91.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 776613 1.32% 92.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4261078 7.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24819499 46.12% 46.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11624197 21.60% 67.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5120039 9.51% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2844700 5.29% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1712935 3.18% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1498439 2.78% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 822147 1.53% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 790849 1.47% 91.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4586490 8.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 58879204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 53819295 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4261078 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4586490 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 202040068 # The number of ROB reads -system.cpu.rob.rob_writes 303073761 # The number of ROB writes -system.cpu.timesIdled 2271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93155 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 184797703 # The number of ROB reads +system.cpu.rob.rob_writes 277819902 # The number of ROB writes +system.cpu.timesIdled 2285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93492 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.797698 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.797698 # CPI: Total CPI of All Threads -system.cpu.ipc 1.253607 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.253607 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 141776374 # number of integer regfile reads -system.cpu.int_regfile_writes 77917804 # number of integer regfile writes -system.cpu.fp_regfile_reads 6238511 # number of floating regfile reads -system.cpu.fp_regfile_writes 6227605 # number of floating regfile writes -system.cpu.misc_regfile_reads 722508 # number of misc regfile reads +system.cpu.cpi 0.719380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.719380 # CPI: Total CPI of All Threads +system.cpu.ipc 1.390086 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.390086 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 139300854 # number of integer regfile reads +system.cpu.int_regfile_writes 75996636 # number of integer regfile writes +system.cpu.fp_regfile_reads 6185785 # number of floating regfile reads +system.cpu.fp_regfile_writes 6053506 # number of floating regfile writes +system.cpu.misc_regfile_reads 715599 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8679 # number of replacements -system.cpu.icache.tagsinuse 1593.583704 # Cycle average of tags in use -system.cpu.icache.total_refs 20379337 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10611 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1920.585901 # Average number of references to valid blocks. +system.cpu.icache.replacements 8657 # number of replacements +system.cpu.icache.tagsinuse 1596.063648 # Cycle average of tags in use +system.cpu.icache.total_refs 19358424 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1827.990935 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.583704 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.778117 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 20379337 # number of ReadReq hits -system.cpu.icache.demand_hits 20379337 # number of demand (read+write) hits -system.cpu.icache.overall_hits 20379337 # number of overall hits -system.cpu.icache.ReadReq_misses 11744 # number of ReadReq misses -system.cpu.icache.demand_misses 11744 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11744 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 187534500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 187534500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 187534500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 20391081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 20391081 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 20391081 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15968.537125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15968.537125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15968.537125 # average overall miss latency +system.cpu.icache.occ_blocks::0 1596.063648 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779328 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 19358424 # number of ReadReq hits +system.cpu.icache.demand_hits 19358424 # number of demand (read+write) hits +system.cpu.icache.overall_hits 19358424 # number of overall hits +system.cpu.icache.ReadReq_misses 11813 # number of ReadReq misses +system.cpu.icache.demand_misses 11813 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11813 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 188211000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 188211000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 188211000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 19370237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 19370237 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 19370237 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000610 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000610 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000610 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15932.531956 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15932.531956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15932.531956 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1133 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1133 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1133 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10611 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10611 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10611 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1223 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1223 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1223 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124781500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124783500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124783500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000520 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000520 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000520 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11759.636227 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000547 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000547 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000547 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11783.144476 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1459.306327 # Cycle average of tags in use -system.cpu.dcache.total_refs 31085202 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13864.942908 # Average number of references to valid blocks. +system.cpu.dcache.replacements 156 # number of replacements +system.cpu.dcache.tagsinuse 1459.699326 # Cycle average of tags in use +system.cpu.dcache.total_refs 30929897 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2239 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13814.156766 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.306327 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356276 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24592075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493081 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 46 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 31085156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 31085156 # number of overall hits -system.cpu.dcache.ReadReq_misses 927 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8022 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1459.699326 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356372 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24436799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 42 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30929855 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30929855 # number of overall hits +system.cpu.dcache.ReadReq_misses 922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8047 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8949 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8949 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28002000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 288506000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8969 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8969 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 27935000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289776500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 316508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 316508000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24593002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 317711500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 317711500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 24437721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 47 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 31094105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 31094105 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30938824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30938824 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001234 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.021277 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000288 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000288 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30207.119741 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35964.348043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.023256 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000290 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000290 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30298.264642 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 36010.500808 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35367.974075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35367.974075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35423.291337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35423.291337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,73 +410,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 418 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6708 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6708 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6315 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2241 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2238 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2238 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61605000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77836000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77836000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77915000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77915000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.021277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.023256 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32043.222004 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35523.094688 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32233.201581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35568.706697 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2396.251917 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7647 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2399.023561 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7622 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.152872 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.145833 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2378.668231 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.583686 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072591 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2381.411279 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.612282 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072675 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 7611 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7661 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7661 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3484 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1708 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5192 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5192 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59253000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178929500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11120 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12853 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12853 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.313309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985574 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.403952 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.403952 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34350.315729 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34691.451991 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34462.538521 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34462.538521 # average overall miss latency +system.cpu.l2cache.demand_hits 7636 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7636 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3486 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5193 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5193 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119743000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59251500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 178994500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 178994500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11097 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12829 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12829 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.314139 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985566 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.404786 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.404786 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34349.684452 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34710.896309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34468.419026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34468.419026 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3484 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5192 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5192 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3486 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5193 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5193 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108359500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162219500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162219500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108417500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53859000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162276500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162276500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313309 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403952 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403952 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.037887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31533.957845 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314139 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.404786 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.404786 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100.831899 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31551.845343 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 788c735d8..00b76845b 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index e55be2152..c549133d9 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 04:01:57 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 19:41:03 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -23,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 109591303500 because target called exit() +122 123 124 Exiting @ tick 108225133500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9acd1c20e..0b4a9f9c5 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.109591 # Number of seconds simulated -sim_ticks 109591303500 # Number of ticks simulated +sim_seconds 0.108225 # Number of seconds simulated +sim_ticks 108225133500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60659 # Simulator instruction rate (inst/s) -host_tick_rate 35235152 # Simulator tick rate (ticks/s) -host_mem_usage 261736 # Number of bytes of host memory used -host_seconds 3110.28 # Real time elapsed on the host -sim_insts 188667697 # Number of instructions simulated +host_inst_rate 75904 # Simulator instruction rate (inst/s) +host_tick_rate 43540817 # Simulator tick rate (ticks/s) +host_mem_usage 267548 # Number of bytes of host memory used +host_seconds 2485.60 # Real time elapsed on the host +sim_insts 188667477 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 219182608 # number of cpu cycles simulated +system.cpu.numCycles 216450268 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103745786 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 81976338 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9943224 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 85671159 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80219991 # Number of BTB hits +system.cpu.BPredUnit.lookups 103300495 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 81633853 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9933179 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 85260221 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79838053 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4756853 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 113204 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 46114245 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429912188 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103745786 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84976844 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 111330567 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35270728 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36699969 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 813 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4770425 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112925 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 45859797 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427202269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103300495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84608478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 110661906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 34687559 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35479219 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 41935754 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2246100 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 219124425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.665143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 41734734 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2307922 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 216391705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.142578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666710 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108000297 49.29% 49.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5031394 2.30% 51.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33002073 15.06% 66.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18529573 8.46% 75.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9301462 4.24% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12648515 5.77% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8577033 3.91% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4456570 2.03% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19577508 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 105933481 48.95% 48.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4813111 2.22% 51.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32934004 15.22% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18446280 8.52% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9282990 4.29% 79.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12615981 5.83% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8571229 3.96% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4380123 2.02% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19414506 8.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 219124425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473330 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.961434 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 55048245 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35099276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102750817 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1404892 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24821195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14312217 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170214 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 436500086 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 694588 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 24821195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 64323611 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 816730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29228849 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 94788839 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5145201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 401098755 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 70910 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2783871 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 682579390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1716423376 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1698124875 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18298501 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298062048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 384517342 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2790601 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2741243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 25505966 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 51358732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18498661 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9149940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5397480 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344257456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2323720 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266454796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 912087 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 155278627 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 378105702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 688088 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 219124425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.215998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.473523 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 216391705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.477248 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.973674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 54721006 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34041868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102087484 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1309075 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24232272 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14250687 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 167114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 433129762 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 697150 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 24232272 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63872072 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611164 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28890421 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 94161740 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4624036 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 397542070 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22398 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2387180 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 678079214 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1699552910 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1681277450 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18275460 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061696 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 380017513 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2786987 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2738977 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 24570466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 49895918 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 17636120 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4759553 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2845254 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 339889742 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2325465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 265876001 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1090686 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 151055977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362148819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 689877 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 216391705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.228679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102187705 46.63% 46.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 39549888 18.05% 64.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35231696 16.08% 80.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 23077585 10.53% 91.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11566082 5.28% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4775373 2.18% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2189017 1.00% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 443166 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 103913 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 100636897 46.51% 46.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 38680237 17.88% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34682486 16.03% 80.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22976662 10.62% 91.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11626624 5.37% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4959669 2.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2310222 1.07% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 416631 0.19% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 102277 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 219124425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 216391705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 343002 18.52% 18.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6054 0.33% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 31 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 2 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 95 0.01% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1162999 62.81% 81.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 339535 18.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 400224 18.78% 18.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5529 0.26% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 59 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 41 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1248313 58.57% 77.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 477105 22.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 207547424 77.89% 77.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926133 0.35% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 6207 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.01% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166254 0.06% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 259347 0.10% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76101 0.03% 78.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 470014 0.18% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207509 0.08% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71627 0.03% 78.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 78.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 42377903 15.90% 94.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14312934 5.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 206820187 77.79% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928873 0.35% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 5969 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33098 0.01% 78.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166620 0.06% 78.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 261178 0.10% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76402 0.03% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 472124 0.18% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207762 0.08% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71816 0.03% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 326 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 42647461 16.04% 94.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14184185 5.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266454796 # Type of FU issued -system.cpu.iq.rate 1.215675 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1851718 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 751012737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 499908383 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 246985878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3785085 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2315100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1843098 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266401517 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1904997 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1061099 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 265876001 # Type of FU issued +system.cpu.iq.rate 1.228347 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2131272 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008016 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 747569642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 491340043 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 245818526 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3796023 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2315934 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1850284 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266096231 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1911042 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1286575 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21507010 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7624 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 380760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5851790 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 20044239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9909 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 389239 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4989293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24821195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25209 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3025 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 346635263 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3972949 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 51358732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 18498661 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2299792 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 339 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 380760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10016813 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1701165 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11717978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 253656328 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 40286910 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12798468 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24232272 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29384 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2101 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342268798 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4011941 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 49895918 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 17636120 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2301609 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 367 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1495 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 389239 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10042133 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1698405 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11740538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 252918304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 40460736 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12957697 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 54087 # number of nop insts executed -system.cpu.iew.exec_refs 54182001 # number of memory reference insts executed -system.cpu.iew.exec_branches 53130827 # Number of branches executed -system.cpu.iew.exec_stores 13895091 # Number of stores executed -system.cpu.iew.exec_rate 1.157283 # Inst execution rate -system.cpu.iew.wb_sent 250510965 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 248828976 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151533747 # num instructions producing a value -system.cpu.iew.wb_consumers 253038401 # num instructions consuming a value +system.cpu.iew.exec_nop 53591 # number of nop insts executed +system.cpu.iew.exec_refs 54201060 # number of memory reference insts executed +system.cpu.iew.exec_branches 52956495 # Number of branches executed +system.cpu.iew.exec_stores 13740324 # Number of stores executed +system.cpu.iew.exec_rate 1.168482 # Inst execution rate +system.cpu.iew.wb_sent 249352337 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 247668810 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150626342 # num instructions producing a value +system.cpu.iew.wb_consumers 251613909 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.135259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598857 # average fanout of values written-back +system.cpu.iew.wb_rate 1.144230 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598641 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188682085 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 157943841 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9804994 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 194303231 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.971070 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.635692 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681865 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 153577683 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635588 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9794361 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 192159434 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.981903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.655341 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109217628 56.21% 56.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 42594648 21.92% 78.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19958113 10.27% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8663175 4.46% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5049927 2.60% 95.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2103639 1.08% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1719455 0.88% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 826115 0.43% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4170531 2.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108154489 56.28% 56.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41572533 21.63% 77.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19548903 10.17% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8803666 4.58% 92.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5118368 2.66% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2098797 1.09% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1631204 0.85% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1005945 0.52% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4225529 2.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 194303231 # Number of insts commited each cycle -system.cpu.commit.count 188682085 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 192159434 # Number of insts commited each cycle +system.cpu.commit.count 188681865 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498593 # Number of memory references committed -system.cpu.commit.loads 29851722 # Number of loads committed +system.cpu.commit.refs 42498505 # Number of memory references committed +system.cpu.commit.loads 29851678 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283920 # Number of branches committed +system.cpu.commit.branches 40283876 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115173 # Number of committed integer instructions. +system.cpu.commit.int_insts 150114997 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4170531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4225529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 536753425 # The number of ROB reads -system.cpu.rob.rob_writes 718144719 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58183 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667697 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667697 # Number of Instructions Simulated -system.cpu.cpi 1.161739 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.161739 # CPI: Total CPI of All Threads -system.cpu.ipc 0.860779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.860779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1134129060 # number of integer regfile reads -system.cpu.int_regfile_writes 413088145 # number of integer regfile writes -system.cpu.fp_regfile_reads 2922495 # number of floating regfile reads -system.cpu.fp_regfile_writes 2493955 # number of floating regfile writes -system.cpu.misc_regfile_reads 519944359 # number of misc regfile reads -system.cpu.misc_regfile_writes 824510 # number of misc regfile writes -system.cpu.icache.replacements 1926 # number of replacements -system.cpu.icache.tagsinuse 1331.949680 # Cycle average of tags in use -system.cpu.icache.total_refs 41931510 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3631 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11548.198843 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 530188252 # The number of ROB reads +system.cpu.rob.rob_writes 708816282 # The number of ROB writes +system.cpu.timesIdled 1726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667477 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667477 # Number of Instructions Simulated +system.cpu.cpi 1.147258 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.147258 # CPI: Total CPI of All Threads +system.cpu.ipc 0.871644 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.871644 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1130629656 # number of integer regfile reads +system.cpu.int_regfile_writes 411782000 # number of integer regfile writes +system.cpu.fp_regfile_reads 2929902 # number of floating regfile reads +system.cpu.fp_regfile_writes 2506543 # number of floating regfile writes +system.cpu.misc_regfile_reads 516287293 # number of misc regfile reads +system.cpu.misc_regfile_writes 824422 # number of misc regfile writes +system.cpu.icache.replacements 1945 # number of replacements +system.cpu.icache.tagsinuse 1331.549144 # Cycle average of tags in use +system.cpu.icache.total_refs 41730466 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3654 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11420.488779 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1331.949680 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.650366 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41931510 # number of ReadReq hits -system.cpu.icache.demand_hits 41931510 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41931510 # number of overall hits -system.cpu.icache.ReadReq_misses 4244 # number of ReadReq misses -system.cpu.icache.demand_misses 4244 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101763500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101763500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101763500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41935754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41935754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41935754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23978.204524 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23978.204524 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23978.204524 # average overall miss latency +system.cpu.icache.occ_blocks::0 1331.549144 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.650170 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41730466 # number of ReadReq hits +system.cpu.icache.demand_hits 41730466 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41730466 # number of overall hits +system.cpu.icache.ReadReq_misses 4268 # number of ReadReq misses +system.cpu.icache.demand_misses 4268 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4268 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101918000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101918000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101918000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41734734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41734734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41734734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23879.568885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23879.568885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23879.568885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,139 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 613 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 613 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 613 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3631 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 614 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 614 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 614 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3654 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3654 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3654 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74668500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74668500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74668500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74785000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20564.169650 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20466.611932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 54 # number of replacements -system.cpu.dcache.tagsinuse 1407.375528 # Cycle average of tags in use -system.cpu.dcache.total_refs 50844385 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1848 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27513.195346 # Average number of references to valid blocks. +system.cpu.dcache.replacements 53 # number of replacements +system.cpu.dcache.tagsinuse 1408.919446 # Cycle average of tags in use +system.cpu.dcache.total_refs 50759192 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1852 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27407.771058 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1407.375528 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343598 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 38435222 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356746 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27773 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24644 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 50791968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 50791968 # number of overall hits -system.cpu.dcache.ReadReq_misses 1795 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7541 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.919446 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343974 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 38350065 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27780 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24600 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 50706812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 50706812 # number of overall hits +system.cpu.dcache.ReadReq_misses 1815 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59271500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236699500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9355 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9355 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59756000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236779500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 295971000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 295971000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 38437017 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 296535500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296535500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 38351880 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27775 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 50801304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 50801304 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 27782 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24600 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 50716167 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 50716167 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.000184 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000184 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33020.334262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31388.343721 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 32923.415978 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31403.116711 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31702.120823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31702.120823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31698.075895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31698.075895 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1035 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1051 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6452 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7488 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7488 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 760 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 7503 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7503 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 764 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1848 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1848 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62524000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62524000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24358000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62603500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62603500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31946.710526 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35151.194853 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31882.198953 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35152.113971 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1932.871986 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1702 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2683 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.634365 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1935.489256 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1725 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2688 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.641741 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1929.817883 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054103 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058893 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1932.435208 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.054049 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058973 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1702 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 1725 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1711 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1711 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2689 # number of ReadReq misses +system.cpu.l2cache.demand_hits 1734 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1734 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1079 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3768 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3768 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92183000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37080500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129263500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129263500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4391 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 3772 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3772 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92325500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37082000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129407500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129407500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1088 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.612389 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 5506 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5506 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.609552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.991728 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.687717 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.687717 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34281.517293 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.616311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.599788 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.599788 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.685071 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.685071 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34283.512811 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34367.006487 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34307.396607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34307.396607 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2680 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1079 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3754 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 3759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3759 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83139500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83299500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 33503500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116643000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116643000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116803000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116803000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.609201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606609 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991728 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.685162 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.685162 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.186916 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.682710 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.682710 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.902985 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 733a1cda5..5bb467c35 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index fbdea3a95..7a3f808a7 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 15 2011 23:50:22 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 17:25:41 +gem5 started Aug 17 2011 17:43:51 +gem5 executing on nadc-0388 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105044494000 because target called exit() +122 123 124 Exiting @ tick 99831779000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index b774063aa..21b77f826 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105044 # Number of seconds simulated -sim_ticks 105044494000 # Number of ticks simulated +sim_seconds 0.099832 # Number of seconds simulated +sim_ticks 99831779000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56697 # Simulator instruction rate (inst/s) -host_tick_rate 26904511 # Simulator tick rate (ticks/s) -host_mem_usage 262296 # Number of bytes of host memory used -host_seconds 3904.35 # Real time elapsed on the host +host_inst_rate 87193 # Simulator instruction rate (inst/s) +host_tick_rate 39323014 # Simulator tick rate (ticks/s) +host_mem_usage 268152 # Number of bytes of host memory used +host_seconds 2538.76 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 210088989 # number of cpu cycles simulated +system.cpu.numCycles 199663559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25906091 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25906091 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2877681 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23697798 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20934390 # Number of BTB hits +system.cpu.BPredUnit.lookups 26033375 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 26033375 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2892272 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23801635 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21124617 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30843739 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261974302 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25906091 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20934390 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70794160 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26721651 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 84571192 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 411 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28839529 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 526028 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 210002245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.077492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.256338 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31432261 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 264493397 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26033375 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 21124617 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 71518034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27440776 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72430048 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 173 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 29258071 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 583239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 199575786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.208704 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313982 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 141083594 67.18% 67.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4096564 1.95% 69.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3267465 1.56% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4473347 2.13% 72.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4273378 2.03% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4452036 2.12% 76.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5454314 2.60% 79.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3065570 1.46% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39835977 18.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129959453 65.12% 65.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4150455 2.08% 67.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3286315 1.65% 68.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4425223 2.22% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4327377 2.17% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4568651 2.29% 75.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5572926 2.79% 78.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3068408 1.54% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 40216978 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 210002245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123310 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.246968 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45814663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73297000 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 55964774 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11133134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23792674 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 424975722 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23792674 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54914820 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 20522213 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23840 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57109649 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53639049 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 413573068 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30245146 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20822120 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 438852783 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1070324075 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1058519342 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11804733 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 199575786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.324695 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45674333 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62083287 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57427578 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10196895 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24193693 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 428380569 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24193693 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54435501 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16645801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21737 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 58104790 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46174264 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 415835044 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22459451 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 21291992 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 441873091 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1077088979 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1065665407 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11423572 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 204489374 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1468 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1462 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108174037 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105166977 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38036544 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 93207180 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32406467 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 401191410 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1447 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281389101 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88945 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 179610706 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 379681728 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 210002245 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.339934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.371545 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 207509682 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1829 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1823 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 98204521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105334480 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37821412 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 75455534 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24783352 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 400833570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 286380326 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 245766 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 179000562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 366769994 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 199575786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.434945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.451491 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69597365 33.14% 33.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 64957213 30.93% 64.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36846366 17.55% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20444772 9.74% 91.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11872646 5.65% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4318388 2.06% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525465 0.73% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 350714 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 89316 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64436357 32.29% 32.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 57784347 28.95% 61.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35429830 17.75% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21049464 10.55% 89.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13197205 6.61% 96.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5079102 2.54% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1923482 0.96% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 545287 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130712 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 210002245 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 199575786 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 107872 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2450287 83.09% 86.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 390701 13.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 94614 3.23% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2515029 85.77% 88.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322713 11.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1204241 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187252248 66.55% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1588066 0.56% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67629899 24.03% 91.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23714647 8.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1207901 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187612443 65.51% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1650340 0.58% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 71566969 24.99% 91.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24342673 8.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281389101 # Type of FU issued -system.cpu.iq.rate 1.339381 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2948860 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770610110 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 574654249 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 273620025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5208142 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6216706 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2514026 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 280509716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2624004 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16305906 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 286380326 # Type of FU issued +system.cpu.iq.rate 1.434314 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2932356 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010239 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770019302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 574569480 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 277218966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5495258 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5820238 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2640122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 285339093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2765688 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17496370 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48517387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5787 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 69063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17520828 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48684890 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26476 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 567154 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17305696 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45289 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45677 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23792674 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 691646 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 425399 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 401192857 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 138630 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105166977 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38036544 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1447 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 309021 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 69063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2486335 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578919 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3065254 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278324671 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66381551 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3064430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24193693 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 457791 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 303468 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 400835397 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134633 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105334480 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37821412 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1827 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 212810 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14667 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 567154 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2502429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 590366 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3092795 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 282646911 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 70091222 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3733415 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89772300 # number of memory reference insts executed -system.cpu.iew.exec_branches 15687599 # Number of branches executed -system.cpu.iew.exec_stores 23390749 # Number of stores executed -system.cpu.iew.exec_rate 1.324794 # Inst execution rate -system.cpu.iew.wb_sent 277184129 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 276134051 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222355020 # num instructions producing a value -system.cpu.iew.wb_consumers 373725319 # num instructions consuming a value +system.cpu.iew.exec_refs 93958027 # number of memory reference insts executed +system.cpu.iew.exec_branches 15691329 # Number of branches executed +system.cpu.iew.exec_stores 23866805 # Number of stores executed +system.cpu.iew.exec_rate 1.415616 # Inst execution rate +system.cpu.iew.wb_sent 281113586 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 279859088 # cumulative count of insts written-back +system.cpu.iew.wb_producers 226653177 # num instructions producing a value +system.cpu.iew.wb_consumers 377782482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.314367 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.594969 # average fanout of values written-back +system.cpu.iew.wb_rate 1.401653 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.599957 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179841994 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 179482154 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2877741 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 186209571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.188784 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.542023 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2892451 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 175382093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.262176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.674972 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71071645 38.17% 38.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70044936 37.62% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18344188 9.85% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12667816 6.80% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5471591 2.94% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2983054 1.60% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2040122 1.10% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1105861 0.59% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2480358 1.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66614816 37.98% 37.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 64778126 36.94% 74.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16236292 9.26% 84.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12183178 6.95% 91.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5701402 3.25% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3006065 1.71% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2037233 1.16% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1096406 0.63% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3728575 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 186209571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 175382093 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2480358 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3728575 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 584934224 # The number of ROB reads -system.cpu.rob.rob_writes 826225881 # The number of ROB writes -system.cpu.timesIdled 1865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 86744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 572498689 # The number of ROB reads +system.cpu.rob.rob_writes 825932723 # The number of ROB writes +system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 87773 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.949070 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.949070 # CPI: Total CPI of All Threads -system.cpu.ipc 1.053663 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.053663 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515807985 # number of integer regfile reads -system.cpu.int_regfile_writes 284258767 # number of integer regfile writes -system.cpu.fp_regfile_reads 3504419 # number of floating regfile reads -system.cpu.fp_regfile_writes 2170248 # number of floating regfile writes -system.cpu.misc_regfile_reads 144660799 # number of misc regfile reads +system.cpu.cpi 0.901973 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.901973 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108680 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.108680 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 526429192 # number of integer regfile reads +system.cpu.int_regfile_writes 287807377 # number of integer regfile writes +system.cpu.fp_regfile_reads 3610412 # number of floating regfile reads +system.cpu.fp_regfile_writes 2295659 # number of floating regfile writes +system.cpu.misc_regfile_reads 148624711 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4219 # number of replacements -system.cpu.icache.tagsinuse 1625.397975 # Cycle average of tags in use -system.cpu.icache.total_refs 28832382 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6182 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4663.924620 # Average number of references to valid blocks. +system.cpu.icache.replacements 4242 # number of replacements +system.cpu.icache.tagsinuse 1597.360420 # Cycle average of tags in use +system.cpu.icache.total_refs 29250473 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6209 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4710.979707 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1625.397975 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.793651 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28832382 # number of ReadReq hits -system.cpu.icache.demand_hits 28832382 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28832382 # number of overall hits -system.cpu.icache.ReadReq_misses 7147 # number of ReadReq misses -system.cpu.icache.demand_misses 7147 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7147 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 169208500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 169208500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 169208500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28839529 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28839529 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28839529 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000248 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000248 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000248 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23675.458234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23675.458234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23675.458234 # average overall miss latency +system.cpu.icache.occ_blocks::0 1597.360420 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779961 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 29250474 # number of ReadReq hits +system.cpu.icache.demand_hits 29250474 # number of demand (read+write) hits +system.cpu.icache.overall_hits 29250474 # number of overall hits +system.cpu.icache.ReadReq_misses 7597 # number of ReadReq misses +system.cpu.icache.demand_misses 7597 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7597 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 175067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 175067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 175067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 29258071 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 29258071 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 29258071 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23044.293800 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23044.293800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23044.293800 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 961 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 961 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 961 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6186 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6186 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6186 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1135 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1135 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1135 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6462 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6462 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6462 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125111000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125815000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125815000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125815000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000214 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000214 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000214 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20224.862593 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19469.978335 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 49 # number of replacements -system.cpu.dcache.tagsinuse 1408.251063 # Cycle average of tags in use -system.cpu.dcache.total_refs 70379715 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1964 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 35834.885438 # Average number of references to valid blocks. +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1414.389130 # Cycle average of tags in use +system.cpu.dcache.total_refs 72873832 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1985 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36712.257935 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.251063 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343811 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 49871091 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508613 # number of WriteReq hits -system.cpu.dcache.demand_hits 70379704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 70379704 # number of overall hits -system.cpu.dcache.ReadReq_misses 713 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7117 # number of WriteReq misses -system.cpu.dcache.demand_misses 7830 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7830 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23577500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 188115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 211693000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 211693000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 49871804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1414.389130 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.345310 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52365835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507475 # number of WriteReq hits +system.cpu.dcache.demand_hits 72873310 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 72873310 # number of overall hits +system.cpu.dcache.ReadReq_misses 884 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8255 # number of WriteReq misses +system.cpu.dcache.demand_misses 9139 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9139 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 27524500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 227342500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 254867000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 254867000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 52366719 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 70387534 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 70387534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33068.022440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26431.853309 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27036.143040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27036.143040 # average overall miss latency +system.cpu.dcache.demand_accesses 72882449 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 72882449 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31136.312217 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27539.975772 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27887.843309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27887.843309 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,72 +369,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5551 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5862 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5862 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 402 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1968 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1968 # number of overall MSHR misses +system.cpu.dcache.writebacks 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 460 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6439 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6899 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6899 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1816 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13701000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 55004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68705000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68705000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 63530000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77603500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77603500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34082.089552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35123.882503 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33192.216981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34983.480176 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2496.142499 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2832 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.754194 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2508.886918 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2866 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3770 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.760212 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2495.127708 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014791 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076145 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2832 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2838 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3751 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128522000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53234000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181756000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6583 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8146 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8146 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.569801 # miss rate for ReadReq accesses +system.cpu.l2cache.occ_blocks::0 2507.064055 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.822864 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076510 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000056 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2865 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2873 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2873 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3766 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 253 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5322 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5322 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128966500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53203000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 182169500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 182169500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 253 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8195 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8195 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567938 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996161 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.651608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.651608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34263.396428 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34190.109184 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34241.899020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34241.899020 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994885 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.649420 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649420 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34244.954859 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.159383 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34229.518978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34229.518978 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3751 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3766 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 253 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5322 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5322 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116406500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48370500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164777000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116813500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7843000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48344500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 165158000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 165158000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569801 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567938 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.651608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.651608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31033.457745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.649420 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649420 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.923526 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31066.473988 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.730077 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |