diff options
Diffstat (limited to 'tests/long/70.twolf')
13 files changed, 1348 insertions, 1341 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 84850f694..e1977cd05 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index d3c569634..90052853e 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 06:59:18 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:47:44 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42094188000 because target called exit() +122 123 124 Exiting @ tick 41833966000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index d48c1814c..e905042e7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042094 # Number of seconds simulated -sim_ticks 42094188000 # Number of ticks simulated +sim_seconds 0.041834 # Number of seconds simulated +sim_ticks 41833966000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121365 # Simulator instruction rate (inst/s) -host_tick_rate 55588778 # Simulator tick rate (ticks/s) -host_mem_usage 196912 # Number of bytes of host memory used -host_seconds 757.24 # Real time elapsed on the host +host_inst_rate 47398 # Simulator instruction rate (inst/s) +host_tick_rate 21575287 # Simulator tick rate (ticks/s) +host_mem_usage 249684 # Number of bytes of host memory used +host_seconds 1938.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 10077672 # ITB hits +system.cpu.itb.fetch_hits 9991202 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10077721 # ITB accesses +system.cpu.itb.fetch_accesses 9991251 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84188377 # number of cpu cycles simulated +system.cpu.numCycles 83667933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83816425 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7701629 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76486748 # Number of cycles cpu stages are processed. -system.cpu.activity 90.851909 # Percentage of cycles cpu is active +system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. +system.cpu.activity 90.796172 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -61,129 +61,129 @@ system.cpu.comFloats 3775974 # Nu system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.916056 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.916056 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091636 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads +system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.091636 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13660151 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 10092693 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4598416 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8981993 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4278316 # Number of BTB hits +system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 131 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.632146 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6418014 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7242137 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73810840 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136386312 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206031 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057919 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38650469 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26688179 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3946440 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 651118 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4597558 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5643144 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 44.894950 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57370437 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26652325 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27496111 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56692266 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.339778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34731944 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49456433 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.744965 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34177132 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 50011245 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.403978 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 66154944 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18033433 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.420336 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30219873 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53968504 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.104459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7205 # number of replacements -system.cpu.icache.tagsinuse 1491.617776 # Cycle average of tags in use -system.cpu.icache.total_refs 10066620 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9090 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1107.438944 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7551 # number of replacements +system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use +system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.617776 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728329 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 10066620 # number of ReadReq hits -system.cpu.icache.demand_hits 10066620 # number of demand (read+write) hits -system.cpu.icache.overall_hits 10066620 # number of overall hits -system.cpu.icache.ReadReq_misses 11049 # number of ReadReq misses -system.cpu.icache.demand_misses 11049 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 285327000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 285327000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 285327000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 10077669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 10077669 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 10077669 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25823.784958 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25823.784958 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25823.784958 # average overall miss latency +system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits +system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits +system.cpu.icache.overall_hits 9979713 # number of overall hits +system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses +system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 13900 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1959 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1959 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1959 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9090 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9090 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9090 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 218831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 218831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 218831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24073.872387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.601089 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491207 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.872245 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.601089 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351953 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995646 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491207 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491207 # number of overall hits -system.cpu.dcache.ReadReq_misses 552 # number of ReadReq misses +system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 26491206 # number of overall hits +system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6094 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6094 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303795000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332185000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332185000 # number of overall miss cycles +system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 6095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses @@ -192,81 +192,81 @@ system.cpu.dcache.ReadReq_miss_rate 0.000028 # mi system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51431.159420 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54816.853122 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54510.173942 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54510.173942 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41040500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49866.950182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3871 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116205000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116205000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53199.084668 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.147121 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6359 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3281 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.938129 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.310088 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.837033 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066263 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6350 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6376 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6376 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3215 # number of ReadReq misses +system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6721 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4937 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4937 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168259500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90562500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258822000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258822000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4938 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11313 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11313 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.336121 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.436401 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.436401 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52335.769829 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52591.463415 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.954426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.954426 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4937 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4937 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129008000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198352500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198352500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.336121 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.436401 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.436401 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40126.905132 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.744483 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9d0ac975a..9b349a51c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index f701d0797..ba1de8238 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:11:56 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 18:07:05 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 34191076000 because target called exit() +122 123 124 Exiting @ tick 32092296500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f1b3177ca..5aa0ca1ff 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.034191 # Number of seconds simulated -sim_ticks 34191076000 # Number of ticks simulated +sim_seconds 0.032092 # Number of seconds simulated +sim_ticks 32092296500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184031 # Simulator instruction rate (inst/s) -host_tick_rate 74747519 # Simulator tick rate (ticks/s) -host_mem_usage 197584 # Number of bytes of host memory used -host_seconds 457.42 # Real time elapsed on the host +host_inst_rate 73581 # Simulator instruction rate (inst/s) +host_tick_rate 28051508 # Simulator tick rate (ticks/s) +host_mem_usage 250560 # Number of bytes of host memory used +host_seconds 1144.05 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24606273 # DTB read hits -system.cpu.dtb.read_misses 355468 # DTB read misses +system.cpu.dtb.read_hits 25665074 # DTB read hits +system.cpu.dtb.read_misses 532377 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 24961741 # DTB read accesses -system.cpu.dtb.write_hits 7276928 # DTB write hits -system.cpu.dtb.write_misses 1204 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7278132 # DTB write accesses -system.cpu.dtb.data_hits 31883201 # DTB hits -system.cpu.dtb.data_misses 356672 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 32239873 # DTB accesses -system.cpu.itb.fetch_hits 17397269 # ITB hits -system.cpu.itb.fetch_misses 74 # ITB misses +system.cpu.dtb.read_accesses 26197451 # DTB read accesses +system.cpu.dtb.write_hits 7413229 # DTB write hits +system.cpu.dtb.write_misses 1159 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7414388 # DTB write accesses +system.cpu.dtb.data_hits 33078303 # DTB hits +system.cpu.dtb.data_misses 533536 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 33611839 # DTB accesses +system.cpu.itb.fetch_hits 19743768 # ITB hits +system.cpu.itb.fetch_misses 86 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 17397343 # ITB accesses +system.cpu.itb.fetch_accesses 19743854 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 68382153 # number of cpu cycles simulated +system.cpu.numCycles 64184594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits +system.cpu.BPredUnit.lookups 19638238 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 14616795 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1934317 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 16315844 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12540710 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1821712 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2747 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 21008427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 166538758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19638238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14362422 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 30824536 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 9451370 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4886757 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 19743768 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 631936 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 64091521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.598452 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.236190 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33266985 51.91% 51.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3147764 4.91% 56.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2102748 3.28% 60.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3556460 5.55% 65.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4397921 6.86% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1522590 2.38% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1866548 2.91% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1731844 2.70% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12498661 19.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 64091521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305965 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.594684 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23134324 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3873003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 28813163 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 914553 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7356478 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3062607 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 160619110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43067 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7356478 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24847542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1029661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 27972484 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2879319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 153930695 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 698435 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1852837 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 113010867 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 199187244 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 187702425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11484819 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 44583506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 529 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 520 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7678386 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 31845410 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9896316 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6196134 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1567027 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 129169470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 502 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107327436 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 534587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 44082208 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35410789 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 113 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 64091521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.674596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23013905 35.91% 35.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13200417 20.60% 56.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9655349 15.06% 71.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7236543 11.29% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5456935 8.51% 91.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2848092 4.44% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1848148 2.88% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 707452 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124680 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 64091521 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206408 12.63% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6500 0.40% 13.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5851 0.36% 13.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 847321 51.84% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 476077 29.13% 94.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91992 5.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 65553727 61.08% 61.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 486899 0.45% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2819079 2.63% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2427572 2.26% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 312395 0.29% 66.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763362 0.71% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27299077 25.44% 92.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7549954 7.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.rate 1.490981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107327436 # Type of FU issued +system.cpu.iq.rate 1.672168 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1634345 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015228 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265519684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 162160015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 94997457 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15395641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 11288937 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7141397 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 100830916 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8130858 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1254132 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11849212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9154 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 349266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3395213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10688 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7356478 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 31189 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 141503695 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 872227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 31845410 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9896316 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 502 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12366 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 349266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1814664 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 342809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2157473 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104568587 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26198042 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2758849 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11194543 # number of nop insts executed -system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed -system.cpu.iew.exec_branches 12448390 # Number of branches executed -system.cpu.iew.exec_stores 7278167 # Number of stores executed -system.cpu.iew.exec_rate 1.455255 # Inst execution rate -system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64595544 # num instructions producing a value -system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.exec_nop 12333723 # number of nop insts executed +system.cpu.iew.exec_refs 33612538 # number of memory reference insts executed +system.cpu.iew.exec_branches 13292388 # Number of branches executed +system.cpu.iew.exec_stores 7414496 # Number of stores executed +system.cpu.iew.exec_rate 1.629185 # Inst execution rate +system.cpu.iew.wb_sent 103278074 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102138854 # cumulative count of insts written-back +system.cpu.iew.wb_producers 68941212 # num instructions producing a value +system.cpu.iew.wb_consumers 95281048 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_rate 1.591330 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.723556 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 49602328 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1920862 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 56735043 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.619864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.379821 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26448220 46.62% 46.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12595125 22.20% 68.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5584191 9.84% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2979320 5.25% 83.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1760489 3.10% 87.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1489209 2.62% 89.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 769969 1.36% 91.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 774387 1.36% 92.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4334133 7.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 56735043 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -287,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4334133 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 186605606 # The number of ROB reads -system.cpu.rob.rob_writes 260771760 # The number of ROB writes -system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 193905253 # The number of ROB reads +system.cpu.rob.rob_writes 290432006 # The number of ROB writes +system.cpu.timesIdled 2283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93073 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads -system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 134796814 # number of integer regfile reads -system.cpu.int_regfile_writes 73485618 # number of integer regfile writes -system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads -system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes -system.cpu.misc_regfile_reads 712206 # number of misc regfile reads +system.cpu.cpi 0.762471 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762471 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311525 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311525 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 141097992 # number of integer regfile reads +system.cpu.int_regfile_writes 77269821 # number of integer regfile writes +system.cpu.fp_regfile_reads 6208793 # number of floating regfile reads +system.cpu.fp_regfile_writes 6125599 # number of floating regfile writes +system.cpu.misc_regfile_reads 715479 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8218 # number of replacements -system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use -system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks. +system.cpu.icache.replacements 8662 # number of replacements +system.cpu.icache.tagsinuse 1591.987817 # Cycle average of tags in use +system.cpu.icache.total_refs 19731988 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1863.266100 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits -system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits -system.cpu.icache.overall_hits 17386201 # number of overall hits -system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses -system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11068 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.occ_blocks::0 1591.987817 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 19731988 # number of ReadReq hits +system.cpu.icache.demand_hits 19731988 # number of demand (read+write) hits +system.cpu.icache.overall_hits 19731988 # number of overall hits +system.cpu.icache.ReadReq_misses 11780 # number of ReadReq misses +system.cpu.icache.demand_misses 11780 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 187835000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 187835000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 187835000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 19743768 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 19743768 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 19743768 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000597 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000597 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000597 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15945.246180 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15945.246180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15945.246180 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,132 +343,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1190 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1190 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1190 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124617500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124617500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124617500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000536 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000536 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000536 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11767.469311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use -system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks. +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1458.064990 # Cycle average of tags in use +system.cpu.dcache.total_refs 30892362 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13785.078983 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30012251 # number of overall hits -system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses -system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1458.064990 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.355973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24399260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493052 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30892312 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30892312 # number of overall hits +system.cpu.dcache.ReadReq_misses 942 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8051 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 8993 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8993 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289250500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 317361500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 317361500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 24400202 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30901305 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30901305 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.019608 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 29841.825902 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35927.276115 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35289.836540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35289.836540 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses +system.cpu.dcache.writebacks 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6318 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 507 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16260000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61635000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77895000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77895000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.019608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32071.005917 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35565.493364 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2392.328540 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7626 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3548 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.149380 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7279 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5098 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2374.739172 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.589369 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072471 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7618 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 7644 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7644 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3480 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5187 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5187 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119535500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59266000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 178801500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 178801500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11098 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12831 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12831 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313570 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.984997 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.404255 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.404255 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34349.281609 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34719.390744 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34471.081550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34471.081550 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3480 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5187 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108240500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53874500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162115000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.404255 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.404255 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.591954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31560.925600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 6ac40b8d3..788c735d8 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 5262b1662..b0302ff58 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 16:39:45 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 04:18:32 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 114583980000 because target called exit() +122 123 124 Exiting @ tick 110281184000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5a112fddd..0fe4beed8 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.114584 # Number of seconds simulated -sim_ticks 114583980000 # Number of ticks simulated +sim_seconds 0.110281 # Number of seconds simulated +sim_ticks 110281184000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37904 # Simulator instruction rate (inst/s) -host_tick_rate 23020273 # Simulator tick rate (ticks/s) -host_mem_usage 259288 # Number of bytes of host memory used -host_seconds 4977.52 # Real time elapsed on the host -sim_insts 188668727 # Number of instructions simulated +host_inst_rate 65382 # Simulator instruction rate (inst/s) +host_tick_rate 38217412 # Simulator tick rate (ticks/s) +host_mem_usage 261804 # Number of bytes of host memory used +host_seconds 2885.63 # Real time elapsed on the host +sim_insts 188667677 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,296 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 229167961 # number of cpu cycles simulated +system.cpu.numCycles 220562369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98244922 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 77066129 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 10346796 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 79994397 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 74750808 # Number of BTB hits +system.cpu.BPredUnit.lookups 104258409 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 82362571 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9936095 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86105898 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80445450 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4424088 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111792 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 36996487 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 401246546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98244922 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79174896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 102059455 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10739700 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 36996487 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2084614 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 229101172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.893988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.602493 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 4758962 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112969 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 46358647 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 433367935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 104258409 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 85204412 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 111822484 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35665794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36992864 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 42110119 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2232853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 220504638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.132131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.672325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 127219261 55.53% 55.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4017584 1.75% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29118578 12.71% 69.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15726187 6.86% 76.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9819635 4.29% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13296507 5.80% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7877710 3.44% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4751479 2.07% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17274231 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108888253 49.38% 49.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4953673 2.25% 51.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33070296 15.00% 66.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18447401 8.37% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9377183 4.25% 79.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12785261 5.80% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8550568 3.88% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4486115 2.03% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19945888 9.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 229101172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.428703 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.750884 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 79313906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32327887 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 94878595 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 682758 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21898026 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14316236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166090 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 406876598 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 708405 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21898026 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 88099979 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 621468 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27861388 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 86740372 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3879939 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 372161493 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 76195 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1579800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 635133998 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1589359787 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1572376571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 16983216 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298063696 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 337070297 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2567300 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2531045 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 20595382 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 47397575 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16557205 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6544934 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4003679 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 318729231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2207616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261466746 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 554929 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 126483137 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 283584721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 571778 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 229101172 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.141272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.407939 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 220504638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.472694 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.964832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 55339748 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35376598 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 103212898 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1403307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 25172087 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14322485 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170339 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 440125451 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 696276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 25172087 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 64672455 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 776963 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29575154 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 95204893 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5103086 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 403993606 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 69868 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2710880 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 687477122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1728388844 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1709997227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18391617 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298062016 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 389415097 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2865354 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2816189 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 26097925 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 51690689 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18730866 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8573671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359744 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346939727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2374386 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267717167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 907172 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 158256505 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 384971202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 738758 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 220504638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.214111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.476414 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108324411 47.28% 47.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46627729 20.35% 67.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34182087 14.92% 82.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22115521 9.65% 92.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11617915 5.07% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4157757 1.81% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1774100 0.77% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 189981 0.08% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111671 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103384796 46.89% 46.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 39397520 17.87% 64.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35187917 15.96% 80.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23179085 10.51% 91.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11803879 5.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4771097 2.16% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2229685 1.01% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 447825 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 102834 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 229101172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 220504638 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 110643 6.25% 6.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5520 0.31% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 24 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1295953 73.23% 79.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 357680 20.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 341650 17.75% 17.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6050 0.31% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 35 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 4 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 93 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1226198 63.72% 81.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 350464 18.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 205127791 78.45% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918034 0.35% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 10104 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 32866 0.01% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166342 0.06% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 251406 0.10% 78.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76052 0.03% 79.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 462257 0.18% 79.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207196 0.08% 79.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71628 0.03% 79.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 79.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40426138 15.46% 94.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13716608 5.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 208615296 77.92% 77.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925342 0.35% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 6202 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33026 0.01% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166299 0.06% 78.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 260522 0.10% 78.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76108 0.03% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 471200 0.18% 78.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207528 0.08% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71629 0.03% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 327 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 42633393 15.92% 94.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14250295 5.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261466746 # Type of FU issued -system.cpu.iq.rate 1.140939 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1769820 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006769 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 750657753 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 445688656 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241497013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3701660 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2110445 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1822638 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 261381402 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1855164 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 983049 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267717167 # Type of FU issued +system.cpu.iq.rate 1.213793 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1924494 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 754979573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 505620151 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 248098864 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3791065 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2339721 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1843061 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267732701 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1908960 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1050657 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17545646 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 453061 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3910128 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21838970 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7625 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 472350 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6083999 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21898026 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16044 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3524 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 320989557 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8588110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 47397575 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16557205 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2183565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 259 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3132 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 453061 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9663378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2166474 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11829852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 247483110 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38551878 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13983636 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 25172087 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44760 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3320 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 349368262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3978827 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 51690689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 18730866 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2350473 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 564 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2427 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 472350 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10008076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1698961 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11707037 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254915521 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 40541135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12801646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 52710 # number of nop insts executed -system.cpu.iew.exec_refs 51991708 # number of memory reference insts executed -system.cpu.iew.exec_branches 51968856 # Number of branches executed -system.cpu.iew.exec_stores 13439830 # Number of stores executed -system.cpu.iew.exec_rate 1.079920 # Inst execution rate -system.cpu.iew.wb_sent 244574618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 243319651 # cumulative count of insts written-back -system.cpu.iew.wb_producers 146548425 # num instructions producing a value -system.cpu.iew.wb_consumers 237755963 # num instructions consuming a value +system.cpu.iew.exec_nop 54149 # number of nop insts executed +system.cpu.iew.exec_refs 54377446 # number of memory reference insts executed +system.cpu.iew.exec_branches 53214768 # Number of branches executed +system.cpu.iew.exec_stores 13836311 # Number of stores executed +system.cpu.iew.exec_rate 1.155753 # Inst execution rate +system.cpu.iew.wb_sent 251638468 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 249941925 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151812393 # num instructions producing a value +system.cpu.iew.wb_consumers 254020317 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.061752 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.616382 # average fanout of values written-back +system.cpu.iew.wb_rate 1.133203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.597639 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188683115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 132297419 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635838 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 10209212 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 207203147 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.910619 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.539035 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188682065 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 160676887 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635628 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9797761 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 195332552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.965953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.628775 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 117680182 56.79% 56.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 47355200 22.85% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20289931 9.79% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8457444 4.08% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5251466 2.53% 96.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1928686 0.93% 96.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2144986 1.04% 98.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 905505 0.44% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3189747 1.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109939001 56.28% 56.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 42858902 21.94% 78.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20127469 10.30% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8563678 4.38% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5111696 2.62% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2060801 1.06% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1694385 0.87% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 852868 0.44% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4123752 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 207203147 # Number of insts commited each cycle -system.cpu.commit.count 188683115 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 195332552 # Number of insts commited each cycle +system.cpu.commit.count 188682065 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42499005 # Number of memory references committed -system.cpu.commit.loads 29851928 # Number of loads committed +system.cpu.commit.refs 42498585 # Number of memory references committed +system.cpu.commit.loads 29851718 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40284126 # Number of branches committed +system.cpu.commit.branches 40283916 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115997 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115157 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3189747 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4123752 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 524988733 # The number of ROB reads -system.cpu.rob.rob_writes 663890510 # The number of ROB writes -system.cpu.timesIdled 1538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 66789 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188668727 # Number of Instructions Simulated -system.cpu.committedInsts_total 188668727 # Number of Instructions Simulated -system.cpu.cpi 1.214658 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.214658 # CPI: Total CPI of All Threads -system.cpu.ipc 0.823277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.823277 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1105306330 # number of integer regfile reads -system.cpu.int_regfile_writes 405513282 # number of integer regfile writes -system.cpu.fp_regfile_reads 2915970 # number of floating regfile reads -system.cpu.fp_regfile_writes 2459492 # number of floating regfile writes -system.cpu.misc_regfile_reads 485972392 # number of misc regfile reads -system.cpu.misc_regfile_writes 824922 # number of misc regfile writes -system.cpu.icache.replacements 1867 # number of replacements -system.cpu.icache.tagsinuse 1275.783892 # Cycle average of tags in use -system.cpu.icache.total_refs 36992467 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3528 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10485.393141 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 540562551 # The number of ROB reads +system.cpu.rob.rob_writes 723954086 # The number of ROB writes +system.cpu.timesIdled 1712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57731 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667677 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667677 # Number of Instructions Simulated +system.cpu.cpi 1.169052 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.169052 # CPI: Total CPI of All Threads +system.cpu.ipc 0.855394 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.855394 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1139481673 # number of integer regfile reads +system.cpu.int_regfile_writes 415646596 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922802 # number of floating regfile reads +system.cpu.fp_regfile_writes 2492399 # number of floating regfile writes +system.cpu.misc_regfile_reads 524104390 # number of misc regfile reads +system.cpu.misc_regfile_writes 824502 # number of misc regfile writes +system.cpu.icache.replacements 1939 # number of replacements +system.cpu.icache.tagsinuse 1330.149475 # Cycle average of tags in use +system.cpu.icache.total_refs 42105837 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3648 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11542.170230 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1275.783892 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.622941 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 36992467 # number of ReadReq hits -system.cpu.icache.demand_hits 36992467 # number of demand (read+write) hits -system.cpu.icache.overall_hits 36992467 # number of overall hits -system.cpu.icache.ReadReq_misses 4020 # number of ReadReq misses -system.cpu.icache.demand_misses 4020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 95473000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 95473000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 95473000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 36996487 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 36996487 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 36996487 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000109 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000109 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000109 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23749.502488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23749.502488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23749.502488 # average overall miss latency +system.cpu.icache.occ_blocks::0 1330.149475 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.649487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 42105837 # number of ReadReq hits +system.cpu.icache.demand_hits 42105837 # number of demand (read+write) hits +system.cpu.icache.overall_hits 42105837 # number of overall hits +system.cpu.icache.ReadReq_misses 4282 # number of ReadReq misses +system.cpu.icache.demand_misses 4282 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 102623500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 102623500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 102623500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 42110119 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 42110119 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 42110119 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23966.254087 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23966.254087 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23966.254087 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,142 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3529 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3529 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3529 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 634 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 634 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 634 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3648 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3648 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3648 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 71843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 71843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 71843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74999500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74999500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74999500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000095 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000095 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000095 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20357.891754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 49 # number of replacements -system.cpu.dcache.tagsinuse 1395.560229 # Cycle average of tags in use -system.cpu.dcache.total_refs 49245913 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1834 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26851.642857 # Average number of references to valid blocks. +system.cpu.dcache.replacements 53 # number of replacements +system.cpu.dcache.tagsinuse 1408.348450 # Cycle average of tags in use +system.cpu.dcache.total_refs 51108076 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1850 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27625.987027 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1395.560229 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.340713 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36836047 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356734 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 28275 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24850 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 49192781 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 49192781 # number of overall hits -system.cpu.dcache.ReadReq_misses 1779 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7553 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.348450 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343835 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 38699028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27661 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24640 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 51055775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 51055775 # number of overall hits +system.cpu.dcache.ReadReq_misses 1814 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9332 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9332 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 57926000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236821500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 294747500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 294747500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36837826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 9354 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9354 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59541500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236790000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 296331500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296331500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 38700842 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 28277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24850 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 49202113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 49202113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000048 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000071 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000190 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000190 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32560.989320 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31354.627300 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31584.601372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31584.601372 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 27663 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 51065129 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 51065129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000183 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000183 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 31679.655762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31679.655762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6461 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6451 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7497 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7497 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 743 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1835 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1835 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1089 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1850 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1850 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23910500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38348500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62259000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24275500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38318500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62594000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32181.022880 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35117.673993 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1850.961242 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1671 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2592 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.644676 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1929.340531 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2692 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.635587 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1847.906973 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054268 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.056394 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1926.279074 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.061457 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058785 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1680 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2600 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3682 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3682 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 89152000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 126314000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 126314000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4271 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1719 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1719 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2698 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3779 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3779 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92484500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37157500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129642000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129642000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4409 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.608757 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.686684 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.686684 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34289.230769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34345.656192 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.812059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.812059 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses 1089 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5498 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5498 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.611930 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.992654 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.687341 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.687341 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34305.901032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34305.901032 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,31 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2584 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3666 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3666 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2683 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 80301000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33586500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 113887500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 113887500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33564500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116951500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116951500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605011 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.683700 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.683700 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31076.238390 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608528 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992654 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.684613 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.684613 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 15faea73a..733a1cda5 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 46cb2af0c..13ca71321 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 9 2011 00:22:05 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 106734154000 because target called exit() +122 123 124 Exiting @ tick 105045070000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 934f22237..05846252d 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,248 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.106734 # Number of seconds simulated -sim_ticks 106734154000 # Number of ticks simulated +sim_seconds 0.105045 # Number of seconds simulated +sim_ticks 105045070000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152335 # Simulator instruction rate (inst/s) -host_tick_rate 73451239 # Simulator tick rate (ticks/s) -host_mem_usage 239116 # Number of bytes of host memory used -host_seconds 1453.13 # Real time elapsed on the host +host_inst_rate 49247 # Simulator instruction rate (inst/s) +host_tick_rate 23369426 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 4494.98 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 213468309 # number of cpu cycles simulated +system.cpu.numCycles 210090141 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25050494 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25050494 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3072725 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 22404993 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 19578906 # Number of BTB hits +system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27480404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261552197 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25050494 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 19578906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 69713468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3100277 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 27480404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 444252 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.014955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.225944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 145514774 68.20% 68.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3945621 1.85% 70.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3133148 1.47% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4337653 2.03% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4594142 2.15% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4407004 2.07% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5010346 2.35% 80.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3238927 1.52% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39197205 18.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.117350 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.225251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66958522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57001085 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 60412397 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5858231 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23148585 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 419968775 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23148585 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 74832356 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 18068346 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22426 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57435303 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 39871804 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 409779933 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21501033 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16352489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 430797248 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1054244247 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1043122682 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11121565 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 196433839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1310 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 83098346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104980766 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37095594 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90430174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30425407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395507957 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281825994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65208 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173816854 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 357698242 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 213378820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.320778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.372811 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72508898 33.98% 33.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 65573468 30.73% 64.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36643591 17.17% 81.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20570957 9.64% 91.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12013670 5.63% 97.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3959812 1.86% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1477782 0.69% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 513095 0.24% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 117547 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 213378820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68694 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2379905 84.54% 86.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 366520 13.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1200241 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187039988 66.37% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1589434 0.56% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68492447 24.30% 91.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23503884 8.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281825994 # Type of FU issued -system.cpu.iq.rate 1.320224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2815119 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774676274 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 563666202 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 273457668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5234861 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5690969 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2532279 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 280803234 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2637638 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16340040 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued +system.cpu.iq.rate 1.342042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48331176 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20419 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16579878 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45973 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23148585 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 533368 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 548562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395509381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 255580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104980766 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37095594 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13059 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2541200 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 744980 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3286180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278309942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67077031 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3516052 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90250007 # number of memory reference insts executed -system.cpu.iew.exec_branches 15873940 # Number of branches executed -system.cpu.iew.exec_stores 23172976 # Number of stores executed -system.cpu.iew.exec_rate 1.303753 # Inst execution rate -system.cpu.iew.wb_sent 277022685 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 275989947 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222941067 # num instructions producing a value -system.cpu.iew.wb_consumers 371922286 # num instructions consuming a value +system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed +system.cpu.iew.exec_branches 15748098 # Number of branches executed +system.cpu.iew.exec_stores 23391917 # Number of stores executed +system.cpu.iew.exec_rate 1.327442 # Inst execution rate +system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222890509 # num instructions producing a value +system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.292885 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599429 # average fanout of values written-back +system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174164320 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3072754 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 190230235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.163658 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.518986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74059520 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 71187215 37.42% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18215863 9.58% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12685132 6.67% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5921003 3.11% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2781558 1.46% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1922219 1.01% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1098236 0.58% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2359489 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 190230235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -252,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2359489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 583398083 # The number of ROB reads -system.cpu.rob.rob_writes 814214435 # The number of ROB writes -system.cpu.timesIdled 1914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 89489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 585604683 # The number of ROB reads +system.cpu.rob.rob_writes 827851683 # The number of ROB writes +system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.964336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.036983 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036983 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516519288 # number of integer regfile reads -system.cpu.int_regfile_writes 284023651 # number of integer regfile writes -system.cpu.fp_regfile_reads 3512884 # number of floating regfile reads -system.cpu.fp_regfile_writes 2186553 # number of floating regfile writes -system.cpu.misc_regfile_reads 145156303 # number of misc regfile reads +system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads +system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516476198 # number of integer regfile reads +system.cpu.int_regfile_writes 284804952 # number of integer regfile writes +system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads +system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes +system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 3419 # number of replacements -system.cpu.icache.tagsinuse 1603.937064 # Cycle average of tags in use -system.cpu.icache.total_refs 27474068 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 5377 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5109.553282 # Average number of references to valid blocks. +system.cpu.icache.replacements 4263 # number of replacements +system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use +system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1603.937064 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.783172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27474068 # number of ReadReq hits -system.cpu.icache.demand_hits 27474068 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27474068 # number of overall hits -system.cpu.icache.ReadReq_misses 6336 # number of ReadReq misses -system.cpu.icache.demand_misses 6336 # number of demand (read+write) misses -system.cpu.icache.overall_misses 6336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 161881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 161881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 161881500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27480404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27480404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27480404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000231 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000231 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000231 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25549.479167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25549.479167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25549.479167 # average overall miss latency +system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits +system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28884352 # number of overall hits +system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses +system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7220 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 957 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 957 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 957 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 5379 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 5379 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 5379 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 120710000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 120710000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 120710000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.tagsinuse 1400.553684 # Cycle average of tags in use -system.cpu.dcache.total_refs 71034499 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36334.782097 # Average number of references to valid blocks. +system.cpu.dcache.replacements 50 # number of replacements +system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use +system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1400.553684 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.341932 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 50525866 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508631 # number of WriteReq hits -system.cpu.dcache.demand_hits 71034497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 71034497 # number of overall hits -system.cpu.dcache.ReadReq_misses 700 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7099 # number of WriteReq misses -system.cpu.dcache.demand_misses 7799 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23034500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 187834000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 210868500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 210868500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 50526566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits +system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 70508699 # number of overall hits +system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses +system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 7819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 71042296 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 71042296 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27037.889473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27037.889473 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5530 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5842 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5842 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 55641500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68917500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2429.026594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2107 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3661 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.575526 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2428.011682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014912 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.074097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2113 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2113 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3657 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5219 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5219 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 125400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53945500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179345500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5764 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2876 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5318 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 7332 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 7332 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.634455 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711811 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34363.958613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34363.958613 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3657 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5219 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5219 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113519000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48964500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162483500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162483500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634455 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.711811 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.711811 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |