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-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini9
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr1
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout13
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr1
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout13
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini9
-rw-r--r--tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr1
-rwxr-xr-xtests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout13
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr2
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout13
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini9
-rw-r--r--tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-timing/stderr2
-rwxr-xr-xtests/long/70.twolf/ref/sparc/linux/simple-timing/stdout13
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt8
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-atomic/stderr2
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-atomic/stdout11
21 files changed, 73 insertions, 87 deletions
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 3d1cca219..9dd2a52cb 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index 36295ae14..8c4b78811 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu
global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
global.BPredUnit.lookups 19468548 # Number of BP lookups
global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
-host_inst_rate 157592 # Simulator instruction rate (inst/s)
-host_mem_usage 206456 # Number of bytes of host memory used
-host_seconds 534.16 # Real time elapsed on the host
-host_tick_rate 76416157 # Simulator tick rate (ticks/s)
+host_inst_rate 134854 # Simulator instruction rate (inst/s)
+host_mem_usage 207240 # Number of bytes of host memory used
+host_seconds 624.23 # Real time elapsed on the host
+host_tick_rate 65390701 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
index 7edb64427..cd7a7fb23 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
index 1669451f7..7f155cd9b 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
@@ -5,13 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:08:21
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:10:53
-M5 executing on piton
+M5 compiled Nov 5 2008 18:30:06
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 21:16:59
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
index 127e45547..f322d0c86 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2451408 # Simulator instruction rate (inst/s)
-host_mem_usage 179100 # Number of bytes of host memory used
-host_seconds 37.49 # Real time elapsed on the host
-host_tick_rate 1225693454 # Simulator tick rate (ticks/s)
+host_inst_rate 5620505 # Simulator instruction rate (inst/s)
+host_mem_usage 198560 # Number of bytes of host memory used
+host_seconds 16.35 # Real time elapsed on the host
+host_tick_rate 2810224606 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
index 7edb64427..cd7a7fb23 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
index f2321006a..e5e1bfe2b 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
@@ -5,13 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:08:21
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:08:38
-M5 executing on piton
+M5 compiled Nov 5 2008 18:30:06
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 19:15:18
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index fdbe4055f..c80a77e5d 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
index 58a892eca..e6e809818 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1888440 # Simulator instruction rate (inst/s)
-host_mem_usage 205224 # Number of bytes of host memory used
-host_seconds 48.67 # Real time elapsed on the host
-host_tick_rate 2440025498 # Simulator tick rate (ticks/s)
+host_inst_rate 1922347 # Simulator instruction rate (inst/s)
+host_mem_usage 206016 # Number of bytes of host memory used
+host_seconds 47.81 # Real time elapsed on the host
+host_tick_rate 2483835101 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118747 # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
index 7edb64427..cd7a7fb23 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
index 2f63f8309..50f9ae74a 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
@@ -5,13 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:08:21
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:14:06
-M5 executing on piton
+M5 compiled Nov 5 2008 18:30:06
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 18:41:43
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
index e8167a62f..0c05fead2 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3028318 # Simulator instruction rate (inst/s)
-host_mem_usage 211228 # Number of bytes of host memory used
-host_seconds 63.88 # Real time elapsed on the host
-host_tick_rate 1514162901 # Simulator tick rate (ticks/s)
+host_inst_rate 2346541 # Simulator instruction rate (inst/s)
+host_mem_usage 200408 # Number of bytes of host memory used
+host_seconds 82.44 # Real time elapsed on the host
+host_tick_rate 1173274177 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.096723 # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
index 7edb64427..5ff857a03 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
index 5631e050f..997da0518 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
@@ -5,13 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:21:24
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:31:36
-M5 executing on piton
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:54:24
+M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 05096323e..afa783463 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
-lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
-split=false
-split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
index 40cd826e7..c4bd23868 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1409829 # Simulator instruction rate (inst/s)
-host_mem_usage 207084 # Number of bytes of host memory used
-host_seconds 137.21 # Real time elapsed on the host
-host_tick_rate 1971980655 # Simulator tick rate (ticks/s)
+host_inst_rate 1243989 # Simulator instruction rate (inst/s)
+host_mem_usage 207864 # Number of bytes of host memory used
+host_seconds 155.50 # Real time elapsed on the host
+host_tick_rate 1740014863 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.270579 # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
index 7edb64427..5ff857a03 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
@@ -1,3 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
index f7be3ede4..98f64dfde 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
@@ -5,13 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 27 2008 21:21:24
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:31:45
-M5 executing on piton
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:41:20
+M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt
index c4fe4712d..2581f730b 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1300052 # Simulator instruction rate (inst/s)
-host_mem_usage 201460 # Number of bytes of host memory used
-host_seconds 168.14 # Real time elapsed on the host
-host_tick_rate 773204086 # Simulator tick rate (ticks/s)
+host_inst_rate 2311586 # Simulator instruction rate (inst/s)
+host_mem_usage 202280 # Number of bytes of host memory used
+host_seconds 94.57 # Real time elapsed on the host
+host_tick_rate 1374811015 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 218595322 # Number of instructions simulated
sim_seconds 0.130009 # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr
index c336b1cb3..27f336eb4 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr
@@ -1,6 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
-warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
index fcbdb82ed..1d99c3015 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
@@ -5,15 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 8 2008 20:20:37
-M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617
-M5 commit date Wed Oct 08 20:18:02 2008 -0700
-M5 started Oct 8 2008 20:20:39
-M5 executing on tater
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 6 2008 00:16:46
+M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program