summaryrefslogtreecommitdiff
path: root/tests/long/70.twolf
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/70.twolf')
-rw-r--r--tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/o3-timing/simout7
-rw-r--r--tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt8
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini5
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-atomic/simerr3
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-atomic/simout22
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt38
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini5
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-timing/simerr3
-rwxr-xr-xtests/long/70.twolf/ref/x86/linux/simple-timing/simout22
-rw-r--r--tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt382
11 files changed, 245 insertions, 252 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index 8802a5811..d20296793 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index ac0a4779d..a8f7791d3 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -3,11 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 16 2011 11:08:03
-gem5 started Nov 17 2011 13:09:16
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
-tests
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 7b2ddaff9..f73117896 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
sim_seconds 0.096690 # Number of seconds simulated
sim_ticks 96689893000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 89575 # Simulator instruction rate (inst/s)
-host_tick_rate 39125952 # Simulator tick rate (ticks/s)
-host_mem_usage 253168 # Number of bytes of host memory used
-host_seconds 2471.25 # Real time elapsed on the host
+host_inst_rate 71082 # Simulator instruction rate (inst/s)
+host_tick_rate 31048201 # Simulator tick rate (ticks/s)
+host_mem_usage 253148 # Number of bytes of host memory used
+host_seconds 3114.19 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 193379787 # number of cpu cycles simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index adbeb371c..22a2b62b1 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -61,12 +62,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
@@ -1,7 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 6d11a44d3..d0fe2b96b 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,16 +1,14 @@
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:38:23
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 80e0c67c1..727d7b7f0 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3098099 # Simulator instruction rate (inst/s)
-host_mem_usage 209904 # Number of bytes of host memory used
-host_seconds 71.45 # Real time elapsed on the host
-host_tick_rate 1838915708 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393100000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 733183 # Simulator instruction rate (inst/s)
+host_tick_rate 435191133 # Simulator tick rate (ticks/s)
+host_mem_usage 241232 # Number of bytes of host memory used
+host_seconds 301.92 # Real time elapsed on the host
+sim_insts 221363018 # Number of instructions simulated
+system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786201 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 262786201 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 221363018 # Number of instructions executed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339607 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
-system.cpu.num_load_insts 56649590 # Number of load instructions
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165306 # number of memory refs
+system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_store_insts 20515716 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 262786201 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 040454ea4..2acc29c81 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -164,12 +165,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
@@ -1,7 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index ac8ab44c7..a9cb69d9f 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,16 +1,14 @@
-M5 Simulator System
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:22:33
-M5 started Apr 19 2011 12:30:33
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
+gem5 compiled Jan 9 2012 14:18:02
+gem5 started Jan 9 2012 14:29:08
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index b2588e568..d8ed7223d 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,223 +1,223 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1944621 # Simulator instruction rate (inst/s)
-host_mem_usage 217656 # Number of bytes of host memory used
-host_seconds 113.83 # Real time elapsed on the host
-host_tick_rate 2204625935 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.250961 # Number of seconds simulated
sim_ticks 250960631000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 461238 # Simulator instruction rate (inst/s)
+host_tick_rate 522908265 # Simulator tick rate (ticks/s)
+host_mem_usage 250008 # Number of bytes of host memory used
+host_seconds 479.93 # Real time elapsed on the host
+sim_insts 221363018 # Number of instructions simulated
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 501921262 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 221363018 # Number of instructions executed
+system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
+system.cpu.num_int_insts 220339607 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
+system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
+system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
+system.cpu.num_mem_refs 77165306 # number of memory refs
+system.cpu.num_load_insts 56649590 # Number of load instructions
+system.cpu.num_store_insts 20515716 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 501921262 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 2836 # number of replacements
+system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
+system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
+system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 173489718 # number of overall hits
+system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
+system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 4694 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 41 # number of replacements
+system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
+system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 77195833 # number of overall hits
+system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
+system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1905 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
+system.cpu.dcache.writebacks 7 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77195833 # number of overall hits
-system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1905 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 7 # number of writebacks
-system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
-system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 173489718 # number of overall hits
-system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4694 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 2836 # number of replacements
-system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
-system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 1864 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 4735 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1864 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4735 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 501921262 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 501921262 # Number of busy cycles
-system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 221363018 # Number of instructions executed
-system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
-system.cpu.num_int_insts 220339607 # number of integer instructions
-system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
-system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
-system.cpu.num_load_insts 56649590 # Number of load instructions
-system.cpu.num_mem_refs 77165306 # number of memory refs
-system.cpu.num_store_insts 20515716 # Number of store instructions
-system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------